1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple ppc64le-linux -ppc-asm-full-reg-names -global-isel -o - < %s \ 3; RUN: | FileCheck %s 4 5; Function Attrs: nounwind readnone 6define i64 @cn15bit1() #0 { 7; CHECK-LABEL: cn15bit1: 8; CHECK: # %bb.0: # %entry 9; CHECK-NEXT: li r3, 32767 10; CHECK-NEXT: blr 11entry: 12 ret i64 32767 13 14} 15 16; Function Attrs: nounwind readnone 17define i64 @cn15bit2() #0 { 18; CHECK-LABEL: cn15bit2: 19; CHECK: # %bb.0: # %entry 20; CHECK-NEXT: li r3, -32767 21; CHECK-NEXT: blr 22entry: 23 ret i64 -32767 24 25} 26 27 28; Function Attrs: nounwind readnone 29define i64 @cn1() #0 { 30; CHECK-LABEL: cn1: 31; CHECK: # %bb.0: # %entry 32; CHECK-NEXT: li r3, -1 33; CHECK-NEXT: rldic r3, r3, 0, 16 34; CHECK-NEXT: blr 35entry: 36 ret i64 281474976710655 37 38} 39 40; Function Attrs: nounwind readnone 41define i64 @cnb() #0 { 42; CHECK-LABEL: cnb: 43; CHECK: # %bb.0: # %entry 44; CHECK-NEXT: li r3, -81 45; CHECK-NEXT: rldic r3, r3, 0, 16 46; CHECK-NEXT: blr 47entry: 48 ret i64 281474976710575 49 50} 51 52; Function Attrs: nounwind readnone 53define i64 @f2(i64 %x) #0 { 54; CHECK-LABEL: f2: 55; CHECK: # %bb.0: # %entry 56; CHECK-NEXT: li r3, -1 57; CHECK-NEXT: rldic r3, r3, 36, 0 58; CHECK-NEXT: blr 59entry: 60 ret i64 -68719476736 61 62} 63 64; Function Attrs: nounwind readnone 65define i64 @f2a(i64 %x) #0 { 66; CHECK-LABEL: f2a: 67; CHECK: # %bb.0: # %entry 68; CHECK-NEXT: li r3, -337 69; CHECK-NEXT: rldic r3, r3, 30, 0 70; CHECK-NEXT: blr 71entry: 72 ret i64 -361850994688 73 74} 75 76; Function Attrs: nounwind readnone 77define i64 @f2n(i64 %x) #0 { 78; CHECK-LABEL: f2n: 79; CHECK: # %bb.0: # %entry 80; CHECK-NEXT: li r3, -1 81; CHECK-NEXT: rldic r3, r3, 0, 28 82; CHECK-NEXT: blr 83entry: 84 ret i64 68719476735 85 86} 87 88; Function Attrs: nounwind readnone 89define i64 @f3(i64 %x) #0 { 90; CHECK-LABEL: f3: 91; CHECK: # %bb.0: # %entry 92; CHECK-NEXT: li r3, -1 93; CHECK-NEXT: rldic r3, r3, 0, 31 94; CHECK-NEXT: blr 95entry: 96 ret i64 8589934591 97 98} 99 100; Function Attrs: nounwind readnone 101define i64 @cn2n() #0 { 102; CHECK-LABEL: cn2n: 103; CHECK: # %bb.0: # %entry 104; CHECK-NEXT: lis r3, -5121 105; CHECK-NEXT: ori r3, r3, 65534 106; CHECK-NEXT: rotldi r3, r3, 22 107; CHECK-NEXT: blr 108entry: 109 ret i64 -1407374887747585 110 111} 112 113define i64 @uint32_1() #0 { 114; CHECK-LABEL: uint32_1: 115; CHECK: # %bb.0: # %entry 116; CHECK-NEXT: li r3, 18176 117; CHECK-NEXT: oris r3, r3, 59509 118; CHECK-NEXT: blr 119entry: 120 ret i64 3900000000 121 122} 123 124define i32 @uint32_1_i32() #0 { 125; CHECK-LABEL: uint32_1_i32: 126; CHECK: # %bb.0: # %entry 127; CHECK-NEXT: lis r3, -6027 128; CHECK-NEXT: ori r3, r3, 18176 129; CHECK-NEXT: blr 130entry: 131 ret i32 -394967296 132 133} 134 135define i64 @uint32_2() #0 { 136; CHECK-LABEL: uint32_2: 137; CHECK: # %bb.0: # %entry 138; CHECK-NEXT: li r3, -1 139; CHECK-NEXT: rldic r3, r3, 0, 32 140; CHECK-NEXT: blr 141entry: 142 ret i64 4294967295 143 144} 145 146define i32 @uint32_2_i32() #0 { 147; CHECK-LABEL: uint32_2_i32: 148; CHECK: # %bb.0: # %entry 149; CHECK-NEXT: li r3, -1 150; CHECK-NEXT: blr 151entry: 152 ret i32 -1 153 154} 155 156define i64 @uint32_3() #0 { 157; CHECK-LABEL: uint32_3: 158; CHECK: # %bb.0: # %entry 159; CHECK-NEXT: li r3, 1 160; CHECK-NEXT: rldic r3, r3, 31, 32 161; CHECK-NEXT: blr 162entry: 163 ret i64 2147483648 164 165} 166 167define i64 @uint32_4() #0 { 168; CHECK-LABEL: uint32_4: 169; CHECK: # %bb.0: # %entry 170; CHECK-NEXT: lis r3, -6027 171; CHECK-NEXT: ori r3, r3, 18177 172; CHECK-NEXT: rldic r3, r3, 5, 27 173; CHECK-NEXT: blr 174entry: 175 ret i64 124800000032 176 177} 178 179define i64 @cn_ones_1() #0 { 180; CHECK-LABEL: cn_ones_1: 181; CHECK: # %bb.0: # %entry 182; CHECK-NEXT: li r3, -25633 183; CHECK-NEXT: rldicl r3, r3, 18, 30 184; CHECK-NEXT: blr 185entry: 186 ret i64 10460594175 187 188} 189 190define i64 @cn_ones_2() #0 { 191; CHECK-LABEL: cn_ones_2: 192; CHECK: # %bb.0: # %entry 193; CHECK-NEXT: lis r3, -25638 194; CHECK-NEXT: ori r3, r3, 24575 195; CHECK-NEXT: rldicl r3, r3, 2, 30 196; CHECK-NEXT: blr 197entry: 198 ret i64 10459119615 199 200} 201 202define i64 @imm1() #0 { 203; CHECK-LABEL: imm1: 204; CHECK: # %bb.0: # %entry 205; CHECK-NEXT: li r3, 8465 206; CHECK-NEXT: rldic r3, r3, 28, 22 207; CHECK-NEXT: blr 208entry: 209 ret i64 2272306135040 ;0x21110000000 210} 211 212define i64 @imm2() #0 { 213; CHECK-LABEL: imm2: 214; CHECK: # %bb.0: # %entry 215; CHECK-NEXT: li r3, -28536 216; CHECK-NEXT: rldicl r3, r3, 1, 32 217; CHECK-NEXT: blr 218entry: 219 ret i64 4294910225 ;0xFFFF2111 220} 221 222define i64 @imm3() #0 { 223; CHECK-LABEL: imm3: 224; CHECK: # %bb.0: # %entry 225; CHECK-NEXT: li r3, -32495 226; CHECK-NEXT: rldic r3, r3, 0, 32 227; CHECK-NEXT: blr 228entry: 229 ret i64 4294934801 ;0xFFFF8111 230} 231 232define i64 @imm4() #0 { 233; CHECK-LABEL: imm4: 234; CHECK: # %bb.0: # %entry 235; CHECK-NEXT: lis r3, 33 236; CHECK-NEXT: ori r3, r3, 4352 237; CHECK-NEXT: rldimi r3, r3, 32, 0 238; CHECK-NEXT: blr 239entry: 240 ret i64 9307365931290880 ;0x21110000211100 241} 242 243define i64 @imm5() #0 { 244; CHECK-LABEL: imm5: 245; CHECK: # %bb.0: # %entry 246; CHECK-NEXT: li r3, 28685 247; CHECK-NEXT: rotldi r3, r3, 52 248; CHECK-NEXT: blr 249entry: 250 ret i64 58546795155816455 ;0xd0000000000007 251} 252 253define i64 @imm6() #0 { 254; CHECK-LABEL: imm6: 255; CHECK: # %bb.0: # %entry 256; CHECK-NEXT: lis r3, -1 257; CHECK-NEXT: ori r3, r3, 28674 258; CHECK-NEXT: rotldi r3, r3, 52 259; CHECK-NEXT: blr 260entry: 261 ret i64 13510798882111479 ;0x2ffffffffffff7 262} 263 264define i64 @imm7() #0 { 265; CHECK-LABEL: imm7: 266; CHECK: # %bb.0: # %entry 267; CHECK-NEXT: li r3, -3823 268; CHECK-NEXT: rldic r3, r3, 28, 20 269; CHECK-NEXT: blr 270entry: 271 ret i64 16565957296128 ;0xf1110000000 272} 273 274define i64 @imm8() #0 { 275; CHECK-LABEL: imm8: 276; CHECK: # %bb.0: # %entry 277; CHECK-NEXT: li r3, -7919 278; CHECK-NEXT: rldic r3, r3, 22, 22 279; CHECK-NEXT: blr 280entry: 281 ret i64 4364831817728 ;0x3f844400000 282} 283 284define i64 @imm9() #0 { 285; CHECK-LABEL: imm9: 286; CHECK: # %bb.0: # %entry 287; CHECK-NEXT: lis r3, -1 288; CHECK-NEXT: ori r3, r3, 28674 289; CHECK-NEXT: rotldi r3, r3, 52 290; CHECK-NEXT: blr 291entry: 292 ret i64 13510798882111479 ;0x2ffffffffffff7 293} 294 295define i64 @imm10() #0 { 296; CHECK-LABEL: imm10: 297; CHECK: # %bb.0: # %entry 298; CHECK-NEXT: li r3, -3823 299; CHECK-NEXT: rldic r3, r3, 28, 20 300; CHECK-NEXT: blr 301entry: 302 ret i64 16565957296128 ;0xf1110000000 303} 304 305define i64 @imm11() #0 { 306; CHECK-LABEL: imm11: 307; CHECK: # %bb.0: # %entry 308; CHECK-NEXT: li r3, -7919 309; CHECK-NEXT: rldic r3, r3, 22, 22 310; CHECK-NEXT: blr 311entry: 312 ret i64 4364831817728 ;0x3f844400000 313} 314 315define i64 @imm12() #0 { 316; CHECK-LABEL: imm12: 317; CHECK: # %bb.0: # %entry 318; CHECK-NEXT: lis r3, -29 319; CHECK-NEXT: ori r3, r3, 64577 320; CHECK-NEXT: rldic r3, r3, 12, 20 321; CHECK-NEXT: blr 322entry: 323 ret i64 17584665923584 ;0xffe3fc41000 324} 325 326define i64 @imm13() #0 { 327; CHECK-LABEL: imm13: 328; CHECK: # %bb.0: # %entry 329; CHECK-NEXT: li r3, -24847 330; CHECK-NEXT: rldicl r3, r3, 21, 27 331; CHECK-NEXT: blr 332entry: 333 ret i64 85333114879 ;0x13de3fffff 334} 335 336define i64 @imm13_2() #0 { 337; CHECK-LABEL: imm13_2: 338; CHECK: # %bb.0: # %entry 339; CHECK-NEXT: li r3, -12424 340; CHECK-NEXT: rldicl r3, r3, 22, 26 341; CHECK-NEXT: blr 342entry: 343 ret i64 222772068351 ;0x33de3fffff 344} 345 346define i64 @imm14() #0 { 347; CHECK-LABEL: imm14: 348; CHECK: # %bb.0: # %entry 349; CHECK-NEXT: li r3, -3960 350; CHECK-NEXT: rldicl r3, r3, 21, 24 351; CHECK-NEXT: blr 352entry: 353 ret i64 1091209003007 ;0xfe111fffff 354} 355 356define i64 @imm15() #0 { 357; CHECK-LABEL: imm15: 358; CHECK: # %bb.0: # %entry 359; CHECK-NEXT: li r3, -8065 360; CHECK-NEXT: rldic r3, r3, 24, 0 361; CHECK-NEXT: blr 362entry: 363 ret i64 -135308247040 364} 365 366define i64 @imm16() #0 { 367; CHECK-LABEL: imm16: 368; CHECK: # %bb.0: # %entry 369; CHECK-NEXT: lis r3, -16392 370; CHECK-NEXT: ori r3, r3, 57217 371; CHECK-NEXT: rldic r3, r3, 16, 0 372; CHECK-NEXT: blr 373entry: 374 ret i64 -70399354142720 375} 376 377define i64 @imm17() #0 { 378; CHECK-LABEL: imm17: 379; CHECK: # %bb.0: # %entry 380; CHECK-NEXT: lis r3, 20344 381; CHECK-NEXT: ori r3, r3, 32847 382; CHECK-NEXT: rotldi r3, r3, 49 383; CHECK-NEXT: blr 384entry: 385 ret i64 44473046320324337 ;0x9e000000009ef1 386} 387 388define i64 @imm18() #0 { 389; CHECK-LABEL: imm18: 390; CHECK: # %bb.0: # %entry 391; CHECK-NEXT: li r3, 1 392; CHECK-NEXT: rldic r3, r3, 33, 30 393; CHECK-NEXT: oris r3, r3, 39436 394; CHECK-NEXT: ori r3, r3, 61633 395; CHECK-NEXT: blr 396entry: 397 ret i64 11174473921 398} 399 400attributes #0 = { nounwind readnone } 401