xref: /llvm-project/llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-arithmentic-vec.ll (revision 3508f123353c0a145ee79cebb972f46fcb97bf1e) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -ppc-vsr-nums-as-vr \
3; RUN:   -ppc-asm-full-reg-names -global-isel -o - < %s | FileCheck %s
4
5define <16 x i8> @test_add_v16i8(<16 x i8> %a, <16 x i8> %b) {
6; CHECK-LABEL: test_add_v16i8:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vaddubm v2, v2, v3
9; CHECK-NEXT:    blr
10  %res = add <16 x i8> %a, %b
11  ret <16 x i8> %res
12}
13
14define <8 x i16> @test_add_v8i16(<8 x i16> %a, <8 x i16> %b) {
15; CHECK-LABEL: test_add_v8i16:
16; CHECK:       # %bb.0:
17; CHECK-NEXT:    vadduhm v2, v2, v3
18; CHECK-NEXT:    blr
19  %res = add <8 x i16> %a, %b
20  ret <8 x i16> %res
21}
22
23define <4 x i32> @test_add_v4i32(<4 x i32> %a, <4 x i32> %b) {
24; CHECK-LABEL: test_add_v4i32:
25; CHECK:       # %bb.0:
26; CHECK-NEXT:    vadduwm v2, v2, v3
27; CHECK-NEXT:    blr
28  %res = add <4 x i32> %a, %b
29  ret <4 x i32> %res
30}
31
32define <2 x i64> @test_add_v2i64(<2 x i64> %a, <2 x i64> %b) {
33; CHECK-LABEL: test_add_v2i64:
34; CHECK:       # %bb.0:
35; CHECK-NEXT:    vaddudm v2, v2, v3
36; CHECK-NEXT:    blr
37  %res = add <2 x i64> %a, %b
38  ret <2 x i64> %res
39}
40
41define <16 x i8> @test_sub_v16i8(<16 x i8> %a, <16 x i8> %b) {
42; CHECK-LABEL: test_sub_v16i8:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    vsububm v2, v2, v3
45; CHECK-NEXT:    blr
46  %res = sub <16 x i8> %a, %b
47  ret <16 x i8> %res
48}
49
50define <8 x i16> @test_sub_v8i16(<8 x i16> %a, <8 x i16> %b) {
51; CHECK-LABEL: test_sub_v8i16:
52; CHECK:       # %bb.0:
53; CHECK-NEXT:    vsubuhm v2, v2, v3
54; CHECK-NEXT:    blr
55  %res = sub <8 x i16> %a, %b
56  ret <8 x i16> %res
57}
58
59define <4 x i32> @test_sub_v4i32(<4 x i32> %a, <4 x i32> %b) {
60; CHECK-LABEL: test_sub_v4i32:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    vsubuwm v2, v2, v3
63; CHECK-NEXT:    blr
64  %res = sub <4 x i32> %a, %b
65  ret <4 x i32> %res
66}
67
68define <2 x i64> @test_sub_v2i64(<2 x i64> %a, <2 x i64> %b) {
69; CHECK-LABEL: test_sub_v2i64:
70; CHECK:       # %bb.0:
71; CHECK-NEXT:    vsubudm v2, v2, v3
72; CHECK-NEXT:    blr
73  %res = sub <2 x i64> %a, %b
74  ret <2 x i64> %res
75}
76