xref: /llvm-project/llvm/test/CodeGen/PowerPC/GlobalISel/fcmp.ll (revision 6a930e889145cbfb3ff1d99f67a5382c19bc1745) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel -o - \
3; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
4
5;; Note that SETUEQ, SETOGE, SETOLE, SETONE, SETULT and SETUGT should be
6;; expanded by DAG legalizer for floating-point types f32 and f64, so there are
7;; no patterns defined in PPCInstrInfo.td file for these setcc patterns for now.
8
9define i1 @fcmp_false(float %a, float %b) {
10; CHECK-LABEL: fcmp_false:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    li r3, 0
13; CHECK-NEXT:    blr
14  %cmp = fcmp false float %a, %b
15  ret i1 %cmp
16}
17
18define i1 @fcmp_oeq(float %a, float %b) {
19; CHECK-LABEL: fcmp_oeq:
20; CHECK:       # %bb.0:
21; CHECK-NEXT:    fcmpu cr0, f1, f2
22; CHECK-NEXT:    li r3, 0
23; CHECK-NEXT:    li r4, 1
24; CHECK-NEXT:    iseleq r3, r4, r3
25; CHECK-NEXT:    blr
26  %cmp = fcmp oeq float %a, %b
27  ret i1 %cmp
28}
29
30define i1 @fcmp_ogt(float %a, float %b) {
31; CHECK-LABEL: fcmp_ogt:
32; CHECK:       # %bb.0:
33; CHECK-NEXT:    fcmpu cr0, f1, f2
34; CHECK-NEXT:    li r3, 0
35; CHECK-NEXT:    li r4, 1
36; CHECK-NEXT:    iselgt r3, r4, r3
37; CHECK-NEXT:    blr
38  %cmp = fcmp ogt float %a, %b
39  ret i1 %cmp
40}
41
42define i1 @fcmp_olt(float %a, float %b) {
43; CHECK-LABEL: fcmp_olt:
44; CHECK:       # %bb.0:
45; CHECK-NEXT:    fcmpu cr0, f1, f2
46; CHECK-NEXT:    li r3, 0
47; CHECK-NEXT:    li r4, 1
48; CHECK-NEXT:    isellt r3, r4, r3
49; CHECK-NEXT:    blr
50  %cmp = fcmp olt float %a, %b
51  ret i1 %cmp
52}
53
54define i1 @fcmp_ord(float %a, float %b) {
55; CHECK-LABEL: fcmp_ord:
56; CHECK:       # %bb.0:
57; CHECK-NEXT:    fcmpu cr0, f1, f2
58; CHECK-NEXT:    li r3, 0
59; CHECK-NEXT:    li r4, 1
60; CHECK-NEXT:    crnot 4*cr5+lt, un
61; CHECK-NEXT:    isel r3, r4, r3, 4*cr5+lt
62; CHECK-NEXT:    blr
63  %cmp = fcmp ord float %a, %b
64  ret i1 %cmp
65}
66
67define i1 @fcmp_uge(float %a, float %b) {
68; CHECK-LABEL: fcmp_uge:
69; CHECK:       # %bb.0:
70; CHECK-NEXT:    fcmpu cr0, f1, f2
71; CHECK-NEXT:    li r3, 0
72; CHECK-NEXT:    li r4, 1
73; CHECK-NEXT:    crnot 4*cr5+lt, lt
74; CHECK-NEXT:    isel r3, r4, r3, 4*cr5+lt
75; CHECK-NEXT:    blr
76  %cmp = fcmp uge float %a, %b
77  ret i1 %cmp
78}
79
80define i1 @fcmp_ule(float %a, float %b) {
81; CHECK-LABEL: fcmp_ule:
82; CHECK:       # %bb.0:
83; CHECK-NEXT:    fcmpu cr0, f1, f2
84; CHECK-NEXT:    li r3, 0
85; CHECK-NEXT:    li r4, 1
86; CHECK-NEXT:    crnot 4*cr5+lt, gt
87; CHECK-NEXT:    isel r3, r4, r3, 4*cr5+lt
88; CHECK-NEXT:    blr
89  %cmp = fcmp ule float %a, %b
90  ret i1 %cmp
91}
92
93define i1 @fcmp_une(float %a, float %b) {
94; CHECK-LABEL: fcmp_une:
95; CHECK:       # %bb.0:
96; CHECK-NEXT:    fcmpu cr0, f1, f2
97; CHECK-NEXT:    li r3, 0
98; CHECK-NEXT:    li r4, 1
99; CHECK-NEXT:    crnot 4*cr5+lt, eq
100; CHECK-NEXT:    isel r3, r4, r3, 4*cr5+lt
101; CHECK-NEXT:    blr
102  %cmp = fcmp une float %a, %b
103  ret i1 %cmp
104}
105
106define i1 @fcmp_uno(float %a, float %b) {
107; CHECK-LABEL: fcmp_uno:
108; CHECK:       # %bb.0:
109; CHECK-NEXT:    fcmpu cr0, f1, f2
110; CHECK-NEXT:    li r3, 0
111; CHECK-NEXT:    li r4, 1
112; CHECK-NEXT:    isel r3, r4, r3, un
113; CHECK-NEXT:    blr
114  %cmp = fcmp uno float %a, %b
115  ret i1 %cmp
116}
117
118define i1 @fcmp_true(float %a, float %b) {
119; CHECK-LABEL: fcmp_true:
120; CHECK:       # %bb.0:
121; CHECK-NEXT:    li r3, 1
122; CHECK-NEXT:    blr
123  %cmp = fcmp true float %a, %b
124  ret i1 %cmp
125}
126
127define i1 @fcmp_false_double(double %a, double %b) {
128; CHECK-LABEL: fcmp_false_double:
129; CHECK:       # %bb.0:
130; CHECK-NEXT:    li r3, 0
131; CHECK-NEXT:    blr
132  %cmp = fcmp false double %a, %b
133  ret i1 %cmp
134}
135
136define i1 @fcmp_oeq_double(double %a, double %b) {
137; CHECK-LABEL: fcmp_oeq_double:
138; CHECK:       # %bb.0:
139; CHECK-NEXT:    fcmpu cr0, f1, f2
140; CHECK-NEXT:    li r3, 0
141; CHECK-NEXT:    li r4, 1
142; CHECK-NEXT:    iseleq r3, r4, r3
143; CHECK-NEXT:    blr
144  %cmp = fcmp oeq double %a, %b
145  ret i1 %cmp
146}
147
148define i1 @fcmp_ogt_double(double %a, double %b) {
149; CHECK-LABEL: fcmp_ogt_double:
150; CHECK:       # %bb.0:
151; CHECK-NEXT:    fcmpu cr0, f1, f2
152; CHECK-NEXT:    li r3, 0
153; CHECK-NEXT:    li r4, 1
154; CHECK-NEXT:    iselgt r3, r4, r3
155; CHECK-NEXT:    blr
156  %cmp = fcmp ogt double %a, %b
157  ret i1 %cmp
158}
159
160define i1 @fcmp_olt_double(double %a, double %b) {
161; CHECK-LABEL: fcmp_olt_double:
162; CHECK:       # %bb.0:
163; CHECK-NEXT:    fcmpu cr0, f1, f2
164; CHECK-NEXT:    li r3, 0
165; CHECK-NEXT:    li r4, 1
166; CHECK-NEXT:    isellt r3, r4, r3
167; CHECK-NEXT:    blr
168  %cmp = fcmp olt double %a, %b
169  ret i1 %cmp
170}
171
172define i1 @fcmp_ord_double(double %a, double %b) {
173; CHECK-LABEL: fcmp_ord_double:
174; CHECK:       # %bb.0:
175; CHECK-NEXT:    fcmpu cr0, f1, f2
176; CHECK-NEXT:    li r3, 0
177; CHECK-NEXT:    li r4, 1
178; CHECK-NEXT:    crnot 4*cr5+lt, un
179; CHECK-NEXT:    isel r3, r4, r3, 4*cr5+lt
180; CHECK-NEXT:    blr
181  %cmp = fcmp ord double %a, %b
182  ret i1 %cmp
183}
184
185define i1 @fcmp_uge_double(double %a, double %b) {
186; CHECK-LABEL: fcmp_uge_double:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    fcmpu cr0, f1, f2
189; CHECK-NEXT:    li r3, 0
190; CHECK-NEXT:    li r4, 1
191; CHECK-NEXT:    crnot 4*cr5+lt, lt
192; CHECK-NEXT:    isel r3, r4, r3, 4*cr5+lt
193; CHECK-NEXT:    blr
194  %cmp = fcmp uge double %a, %b
195  ret i1 %cmp
196}
197
198define i1 @fcmp_ule_double(double %a, double %b) {
199; CHECK-LABEL: fcmp_ule_double:
200; CHECK:       # %bb.0:
201; CHECK-NEXT:    fcmpu cr0, f1, f2
202; CHECK-NEXT:    li r3, 0
203; CHECK-NEXT:    li r4, 1
204; CHECK-NEXT:    crnot 4*cr5+lt, gt
205; CHECK-NEXT:    isel r3, r4, r3, 4*cr5+lt
206; CHECK-NEXT:    blr
207  %cmp = fcmp ule double %a, %b
208  ret i1 %cmp
209}
210
211define i1 @fcmp_une_double(double %a, double %b) {
212; CHECK-LABEL: fcmp_une_double:
213; CHECK:       # %bb.0:
214; CHECK-NEXT:    fcmpu cr0, f1, f2
215; CHECK-NEXT:    li r3, 0
216; CHECK-NEXT:    li r4, 1
217; CHECK-NEXT:    crnot 4*cr5+lt, eq
218; CHECK-NEXT:    isel r3, r4, r3, 4*cr5+lt
219; CHECK-NEXT:    blr
220  %cmp = fcmp une double %a, %b
221  ret i1 %cmp
222}
223
224define i1 @fcmp_uno_double(double %a, double %b) {
225; CHECK-LABEL: fcmp_uno_double:
226; CHECK:       # %bb.0:
227; CHECK-NEXT:    fcmpu cr0, f1, f2
228; CHECK-NEXT:    li r3, 0
229; CHECK-NEXT:    li r4, 1
230; CHECK-NEXT:    isel r3, r4, r3, un
231; CHECK-NEXT:    blr
232  %cmp = fcmp uno double %a, %b
233  ret i1 %cmp
234}
235
236define i1 @fcmp_true_double(double %a, double %b) {
237; CHECK-LABEL: fcmp_true_double:
238; CHECK:       # %bb.0:
239; CHECK-NEXT:    li r3, 1
240; CHECK-NEXT:    blr
241  %cmp = fcmp true double %a, %b
242  ret i1 %cmp
243}
244