xref: /llvm-project/llvm/test/CodeGen/PowerPC/2006-08-11-RetVector.ll (revision 300e1293de635adbe651030de5c8ebd3263458b2)
1; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 -ppc-disable-perfect-shuffle=false | grep vsldoi
2; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 -ppc-disable-perfect-shuffle=false | not grep vor
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4; TODO: Fix this case when disabling perfect shuffle
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6define <4 x float> @func(<4 x float> %fp0, <4 x float> %fp1) {
7        %tmp76 = shufflevector <4 x float> %fp0, <4 x float> %fp1, <4 x i32> < i32 0, i32 1, i32 2, i32 7 >     ; <<4 x float>> [#uses=1]
8        ret <4 x float> %tmp76
9}
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