1; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_20 | FileCheck %s 2; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_20 | %ptxas-verify %} 3 4target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" 5 6define <16 x float> @test_v16f32(<16 x float> %a) { 7; CHECK-LABEL: test_v16f32( 8; CHECK-DAG: ld.param.v4.f32 {[[V_12_15:(%f[0-9]+[, ]*){4}]]}, [test_v16f32_param_0+48]; 9; CHECK-DAG: ld.param.v4.f32 {[[V_8_11:(%f[0-9]+[, ]*){4}]]}, [test_v16f32_param_0+32]; 10; CHECK-DAG: ld.param.v4.f32 {[[V_4_7:(%f[0-9]+[, ]*){4}]]}, [test_v16f32_param_0+16]; 11; CHECK-DAG: ld.param.v4.f32 {[[V_0_3:(%f[0-9]+[, ]*){4}]]}, [test_v16f32_param_0]; 12; CHECK-DAG: st.param.v4.f32 [func_retval0], {[[V_0_3]]} 13; CHECK-DAG: st.param.v4.f32 [func_retval0+16], {[[V_4_7]]} 14; CHECK-DAG: st.param.v4.f32 [func_retval0+32], {[[V_8_11]]} 15; CHECK-DAG: st.param.v4.f32 [func_retval0+48], {[[V_12_15]]} 16; CHECK: ret; 17 ret <16 x float> %a 18} 19 20define <8 x float> @test_v8f32(<8 x float> %a) { 21; CHECK-LABEL: test_v8f32( 22; CHECK-DAG: ld.param.v4.f32 {[[V_4_7:(%f[0-9]+[, ]*){4}]]}, [test_v8f32_param_0+16]; 23; CHECK-DAG: ld.param.v4.f32 {[[V_0_3:(%f[0-9]+[, ]*){4}]]}, [test_v8f32_param_0]; 24; CHECK-DAG: st.param.v4.f32 [func_retval0], {[[V_0_3]]} 25; CHECK-DAG: st.param.v4.f32 [func_retval0+16], {[[V_4_7]]} 26; CHECK: ret; 27 ret <8 x float> %a 28} 29 30define <4 x float> @test_v4f32(<4 x float> %a) { 31; CHECK-LABEL: test_v4f32( 32; CHECK-DAG: ld.param.v4.f32 {[[V_0_3:(%f[0-9]+[, ]*){4}]]}, [test_v4f32_param_0]; 33; CHECK-DAG: st.param.v4.f32 [func_retval0], {[[V_0_3]]} 34; CHECK: ret; 35 ret <4 x float> %a 36} 37 38define <2 x float> @test_v2f32(<2 x float> %a) { 39; CHECK-LABEL: test_v2f32( 40; CHECK-DAG: ld.param.v2.f32 {[[V_0_3:(%f[0-9]+[, ]*){2}]]}, [test_v2f32_param_0]; 41; CHECK-DAG: st.param.v2.f32 [func_retval0], {[[V_0_3]]} 42; CHECK: ret; 43 ret <2 x float> %a 44} 45 46; Oddly shaped vectors should not load any extra elements. 47define <3 x float> @test_v3f32(<3 x float> %a) { 48; CHECK-LABEL: test_v3f32( 49; CHECK-DAG: ld.param.f32 [[V_2:%f[0-9]+]], [test_v3f32_param_0+8]; 50; CHECK-DAG: ld.param.v2.f32 {[[V_0_1:(%f[0-9]+[, ]*){2}]]}, [test_v3f32_param_0]; 51; CHECK-DAG: st.param.v2.f32 [func_retval0], {[[V_0_1]]} 52; CHECK-DAG: st.param.f32 [func_retval0+8], [[V_2]] 53; CHECK: ret; 54 ret <3 x float> %a 55} 56 57define <8 x i64> @test_v8i64(<8 x i64> %a) { 58; CHECK-LABEL: test_v8i64( 59; CHECK-DAG: ld.param.v2.u64 {[[V_6_7:(%rd[0-9]+[, ]*){2}]]}, [test_v8i64_param_0+48]; 60; CHECK-DAG: ld.param.v2.u64 {[[V_4_5:(%rd[0-9]+[, ]*){2}]]}, [test_v8i64_param_0+32]; 61; CHECK-DAG: ld.param.v2.u64 {[[V_2_3:(%rd[0-9]+[, ]*){2}]]}, [test_v8i64_param_0+16]; 62; CHECK-DAG: ld.param.v2.u64 {[[V_0_1:(%rd[0-9]+[, ]*){2}]]}, [test_v8i64_param_0]; 63; CHECK-DAG: st.param.v2.b64 [func_retval0], {[[V_0_1]]} 64; CHECK-DAG: st.param.v2.b64 [func_retval0+16], {[[V_2_3]]} 65; CHECK-DAG: st.param.v2.b64 [func_retval0+32], {[[V_4_5]]} 66; CHECK-DAG: st.param.v2.b64 [func_retval0+48], {[[V_6_7]]} 67; CHECK: ret; 68 ret <8 x i64> %a 69} 70 71define <16 x i16> @test_v16i16(<16 x i16> %a) { 72; CHECK-LABEL: test_v16i16( 73; CHECK-DAG: ld.param.v4.u32 {[[V_8_15:(%r[0-9]+[, ]*){4}]]}, [test_v16i16_param_0+16]; 74; CHECK-DAG: ld.param.v4.u32 {[[V_0_7:(%r[0-9]+[, ]*){4}]]}, [test_v16i16_param_0]; 75; CHECK-DAG: st.param.v4.b32 [func_retval0], {[[V_0_7]]} 76; CHECK-DAG: st.param.v4.b32 [func_retval0+16], {[[V_8_15]]} 77; CHECK: ret; 78 ret <16 x i16> %a 79} 80