1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_20 -verify-machineinstrs | FileCheck %s 3; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_30 -verify-machineinstrs | FileCheck %s 4; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %} 5; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_30 -verify-machineinstrs | %ptxas-verify %} 6 7target triple = "nvptx-unknown-cuda" 8 9declare i32 @llvm.nvvm.suld.1d.i32.trap(i64, i32) 10declare i64 @llvm.nvvm.texsurf.handle.internal.p1(ptr addrspace(1)) 11 12 13define ptx_kernel void @foo(i64 %img, ptr %red, i32 %idx) { 14; CHECK-LABEL: foo( 15; CHECK: { 16; CHECK-NEXT: .reg .b32 %r<3>; 17; CHECK-NEXT: .reg .f32 %f<2>; 18; CHECK-NEXT: .reg .b64 %rd<4>; 19; CHECK-EMPTY: 20; CHECK-NEXT: // %bb.0: 21; CHECK-NEXT: ld.param.u64 %rd1, [foo_param_0]; 22; CHECK-NEXT: ld.param.u64 %rd2, [foo_param_1]; 23; CHECK-NEXT: cvta.to.global.u64 %rd3, %rd2; 24; CHECK-NEXT: ld.param.u32 %r1, [foo_param_2]; 25; CHECK-NEXT: suld.b.1d.b32.trap {%r2}, [%rd1, {%r1}]; 26; CHECK-NEXT: cvt.rn.f32.s32 %f1, %r2; 27; CHECK-NEXT: st.global.f32 [%rd3], %f1; 28; CHECK-NEXT: ret; 29 %val = tail call i32 @llvm.nvvm.suld.1d.i32.trap(i64 %img, i32 %idx) 30 %ret = sitofp i32 %val to float 31 store float %ret, ptr %red 32 ret void 33} 34 35@surf0 = internal addrspace(1) global i64 0, align 8 36 37define ptx_kernel void @bar(ptr %red, i32 %idx) { 38; CHECK-LABEL: bar( 39; CHECK: { 40; CHECK-NEXT: .reg .b32 %r<3>; 41; CHECK-NEXT: .reg .f32 %f<2>; 42; CHECK-NEXT: .reg .b64 %rd<4>; 43; CHECK-EMPTY: 44; CHECK-NEXT: // %bb.0: 45; CHECK-NEXT: ld.param.u64 %rd1, [bar_param_0]; 46; CHECK-NEXT: cvta.to.global.u64 %rd2, %rd1; 47; CHECK-NEXT: ld.param.u32 %r1, [bar_param_1]; 48; CHECK-NEXT: suld.b.1d.b32.trap {%r2}, [surf0, {%r1}]; 49; CHECK-NEXT: cvt.rn.f32.s32 %f1, %r2; 50; CHECK-NEXT: st.global.f32 [%rd2], %f1; 51; CHECK-NEXT: ret; 52 %surfHandle = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1(ptr addrspace(1) @surf0) 53 %val = tail call i32 @llvm.nvvm.suld.1d.i32.trap(i64 %surfHandle, i32 %idx) 54 %ret = sitofp i32 %val to float 55 store float %ret, ptr %red 56 ret void 57} 58 59!nvvm.annotations = !{!1} 60!1 = !{ptr addrspace(1) @surf0, !"surface", i32 1} 61