1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_20 | FileCheck %s 3 4target triple = "nvptx-nvidia-cuda" 5 6define <6 x half> @half6() { 7; CHECK-LABEL: half6( 8; CHECK: { 9; CHECK-NEXT: .reg .b16 %rs<2>; 10; CHECK-EMPTY: 11; CHECK-NEXT: // %bb.0: 12; CHECK-NEXT: mov.b16 %rs1, 0x0000; 13; CHECK-NEXT: st.param.v4.b16 [func_retval0], {%rs1, %rs1, %rs1, %rs1}; 14; CHECK-NEXT: st.param.v2.b16 [func_retval0+8], {%rs1, %rs1}; 15; CHECK-NEXT: ret; 16 ret <6 x half> zeroinitializer 17} 18 19define <10 x half> @half10() { 20; CHECK-LABEL: half10( 21; CHECK: { 22; CHECK-NEXT: .reg .b16 %rs<2>; 23; CHECK-EMPTY: 24; CHECK-NEXT: // %bb.0: 25; CHECK-NEXT: mov.b16 %rs1, 0x0000; 26; CHECK-NEXT: st.param.v4.b16 [func_retval0], {%rs1, %rs1, %rs1, %rs1}; 27; CHECK-NEXT: st.param.v4.b16 [func_retval0+8], {%rs1, %rs1, %rs1, %rs1}; 28; CHECK-NEXT: st.param.v2.b16 [func_retval0+16], {%rs1, %rs1}; 29; CHECK-NEXT: ret; 30 ret <10 x half> zeroinitializer 31} 32 33define <12 x i8> @byte12() { 34; CHECK-LABEL: byte12( 35; CHECK: { 36; CHECK-NEXT: .reg .b16 %rs<2>; 37; CHECK-EMPTY: 38; CHECK-NEXT: // %bb.0: 39; CHECK-NEXT: mov.b16 %rs1, 0; 40; CHECK-NEXT: st.param.v4.b8 [func_retval0], {%rs1, %rs1, %rs1, %rs1}; 41; CHECK-NEXT: st.param.v4.b8 [func_retval0+4], {%rs1, %rs1, %rs1, %rs1}; 42; CHECK-NEXT: st.param.v4.b8 [func_retval0+8], {%rs1, %rs1, %rs1, %rs1}; 43; CHECK-NEXT: ret; 44 ret <12 x i8> zeroinitializer 45} 46 47define <20 x i8> @byte20() { 48; CHECK-LABEL: byte20( 49; CHECK: { 50; CHECK-NEXT: .reg .b16 %rs<2>; 51; CHECK-EMPTY: 52; CHECK-NEXT: // %bb.0: 53; CHECK-NEXT: mov.b16 %rs1, 0; 54; CHECK-NEXT: st.param.v4.b8 [func_retval0], {%rs1, %rs1, %rs1, %rs1}; 55; CHECK-NEXT: st.param.v4.b8 [func_retval0+4], {%rs1, %rs1, %rs1, %rs1}; 56; CHECK-NEXT: st.param.v4.b8 [func_retval0+8], {%rs1, %rs1, %rs1, %rs1}; 57; CHECK-NEXT: st.param.v4.b8 [func_retval0+12], {%rs1, %rs1, %rs1, %rs1}; 58; CHECK-NEXT: st.param.v4.b8 [func_retval0+16], {%rs1, %rs1, %rs1, %rs1}; 59; CHECK-NEXT: ret; 60 ret <20 x i8> zeroinitializer 61} 62