xref: /llvm-project/llvm/test/CodeGen/Mips/setne.ll (revision ae26f50aea4ef1a6c7058019f0db11a91bbcdade)
1; RUN: llc  -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
2; RUN: llc  -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
3
4@i = global i32 1, align 4
5@j = global i32 10, align 4
6@k = global i32 1, align 4
7@r1 = common global i32 0, align 4
8@r2 = common global i32 0, align 4
9
10define void @test() nounwind {
11entry:
12  %0 = load i32, ptr @i, align 4
13  %1 = load i32, ptr @k, align 4
14  %cmp = icmp ne i32 %0, %1
15  %conv = zext i1 %cmp to i32
16  store i32 %conv, ptr @r1, align 4
17; 16:   xor     $[[REGISTER:[0-9]+]], ${{[0-9]+}}
18; 16:   sltu    ${{[0-9]+}}, $[[REGISTER]]
19; MMR6: sltu    ${{[0-9]+}}, $zero, ${{[0-9]+}}
20; 16:   move    ${{[0-9]+}}, $24
21  ret void
22}
23