xref: /llvm-project/llvm/test/CodeGen/Mips/setge.ll (revision ae26f50aea4ef1a6c7058019f0db11a91bbcdade)
1; RUN: llc  -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
2; RUN: llc  -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
3
4@j = global i32 -5, align 4
5@k = global i32 10, align 4
6@l = global i32 20, align 4
7@m = global i32 10, align 4
8@r1 = common global i32 0, align 4
9@r2 = common global i32 0, align 4
10@r3 = common global i32 0, align 4
11@.str = private unnamed_addr constant [22 x i8] c"1 = %i\0A1 = %i\0A0 = %i\0A\00", align 1
12
13define void @test() nounwind {
14entry:
15  %0 = load i32, ptr @k, align 4
16  %1 = load i32, ptr @j, align 4
17  %cmp = icmp sge i32 %0, %1
18  %conv = zext i1 %cmp to i32
19  store i32 %conv, ptr @r1, align 4
20; 16:   slt   ${{[0-9]+}}, ${{[0-9]+}}
21; MMR6: slt   ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
22; 16:   move  $[[REGISTER:[0-9]+]], $24
23; 16:   xor   $[[REGISTER]], ${{[0-9]+}}
24  %2 = load i32, ptr @m, align 4
25  %cmp1 = icmp sge i32 %0, %2
26  %conv2 = zext i1 %cmp1 to i32
27  store i32 %conv2, ptr @r2, align 4
28  ret void
29}
30