1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=mipsel-linux-gnu -mattr=+micromips -relocation-model=pic < %s | FileCheck %s 3 4; Test that the delay slot filler correctly handles indirect branches for 5; microMIPS in regard to incorrectly using 16bit instructions in delay slots of 6; 32bit instructions. 7 8define i32 @test(i32 signext %x, i32 signext %c) { 9; CHECK-LABEL: test: 10; CHECK: # %bb.0: # %entry 11; CHECK-NEXT: lui $2, %hi(_gp_disp) 12; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp) 13; CHECK-NEXT: addiur2 $5, $5, -1 14; CHECK-NEXT: sltiu $1, $5, 4 15; CHECK-NEXT: beqz $1, $BB0_6 16; CHECK-NEXT: addu $3, $2, $25 17; CHECK-NEXT: # %bb.1: # %entry 18; CHECK-NEXT: li16 $2, 0 19; CHECK-NEXT: sll16 $5, $5, 2 20; CHECK-NEXT: lw $6, %got($JTI0_0)($3) 21; CHECK-NEXT: addu16 $5, $5, $6 22; CHECK-NEXT: lw $5, %lo($JTI0_0)($5) 23; CHECK-NEXT: addu16 $3, $5, $3 24; CHECK-NEXT: jr $3 25; CHECK-NEXT: nop 26; CHECK-NEXT: $BB0_2: # %sw.bb2 27; CHECK-NEXT: addiur2 $2, $4, 1 28; CHECK-NEXT: jrc $ra 29; CHECK-NEXT: $BB0_3: # %sw.bb3 30; CHECK-NEXT: addius5 $4, 2 31; CHECK-NEXT: move $2, $4 32; CHECK-NEXT: jrc $ra 33; CHECK-NEXT: $BB0_4: # %sw.bb5 34; CHECK-NEXT: addius5 $4, 3 35; CHECK-NEXT: move $2, $4 36; CHECK-NEXT: $BB0_5: # %for.cond.cleanup 37; CHECK-NEXT: jrc $ra 38; CHECK-NEXT: $BB0_6: 39; CHECK-NEXT: move $2, $4 40; CHECK-NEXT: jrc $ra 41entry: 42 switch i32 %c, label %sw.epilog [ 43 i32 4, label %sw.bb5 44 i32 1, label %for.cond.cleanup 45 i32 2, label %sw.bb2 46 i32 3, label %sw.bb3 47 ] 48 49sw.bb2: 50 %add = add nsw i32 %x, 1 51 br label %sw.epilog 52 53sw.bb3: 54 %add4 = add nsw i32 %x, 2 55 br label %sw.epilog 56 57sw.bb5: 58 %add6 = add nsw i32 %x, 3 59 br label %sw.epilog 60 61sw.epilog: 62 %a.0 = phi i32 [ %add6, %sw.bb5 ], [ %add4, %sw.bb3 ], [ %add, %sw.bb2 ], [ %x, %entry ] 63 br label %for.cond.cleanup 64 65for.cond.cleanup: 66 %a.028 = phi i32 [ %a.0, %sw.epilog ], [ 0, %entry ] 67 ret i32 %a.028 68} 69