1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2;; Test the strict-align feature which is similar to AArch64/arm64-strict-align.ll. 3 4; RUN: llc --mtriple=mipsisa32r6 < %s | FileCheck %s --check-prefix=MIPS32R6-UNALIGNED 5; RUN: llc --mtriple=mipsisa32r6 --mattr=-strict-align < %s | FileCheck %s --check-prefix=MIPS32R6-UNALIGNED 6; RUN: llc --mtriple=mipsisa32r6 --mattr=+strict-align < %s | FileCheck %s --check-prefix=MIPS32R6-ALIGNED 7 8; RUN: llc --mtriple=mipsisa64r6 < %s | FileCheck %s --check-prefix=MIPS64R6-UNALIGNED 9; RUN: llc --mtriple=mipsisa64r6 --mattr=-strict-align < %s | FileCheck %s --check-prefix=MIPS64R6-UNALIGNED 10; RUN: llc --mtriple=mipsisa64r6 --mattr=+strict-align < %s | FileCheck %s --check-prefix=MIPS64R6-ALIGNED 11 12define i32 @f0(ptr %p) nounwind { 13; MIPS32R6-UNALIGNED-LABEL: f0: 14; MIPS32R6-UNALIGNED: # %bb.0: 15; MIPS32R6-UNALIGNED-NEXT: lw $2, 0($4) 16; MIPS32R6-UNALIGNED-NEXT: jrc $ra 17; 18; MIPS32R6-ALIGNED-LABEL: f0: 19; MIPS32R6-ALIGNED: # %bb.0: 20; MIPS32R6-ALIGNED-NEXT: lhu $1, 2($4) 21; MIPS32R6-ALIGNED-NEXT: lhu $2, 0($4) 22; MIPS32R6-ALIGNED-NEXT: sll $2, $2, 16 23; MIPS32R6-ALIGNED-NEXT: jr $ra 24; MIPS32R6-ALIGNED-NEXT: or $2, $2, $1 25; 26; MIPS64R6-UNALIGNED-LABEL: f0: 27; MIPS64R6-UNALIGNED: # %bb.0: 28; MIPS64R6-UNALIGNED-NEXT: lw $2, 0($4) 29; MIPS64R6-UNALIGNED-NEXT: jrc $ra 30; 31; MIPS64R6-ALIGNED-LABEL: f0: 32; MIPS64R6-ALIGNED: # %bb.0: 33; MIPS64R6-ALIGNED-NEXT: lhu $1, 2($4) 34; MIPS64R6-ALIGNED-NEXT: lhu $2, 0($4) 35; MIPS64R6-ALIGNED-NEXT: sll $2, $2, 16 36; MIPS64R6-ALIGNED-NEXT: jr $ra 37; MIPS64R6-ALIGNED-NEXT: or $2, $2, $1 38 %tmp = load i32, ptr %p, align 2 39 ret i32 %tmp 40} 41 42define i64 @f1(ptr %p) nounwind { 43; MIPS32R6-UNALIGNED-LABEL: f1: 44; MIPS32R6-UNALIGNED: # %bb.0: 45; MIPS32R6-UNALIGNED-NEXT: lw $2, 0($4) 46; MIPS32R6-UNALIGNED-NEXT: lw $3, 4($4) 47; MIPS32R6-UNALIGNED-NEXT: jrc $ra 48; 49; MIPS32R6-ALIGNED-LABEL: f1: 50; MIPS32R6-ALIGNED: # %bb.0: 51; MIPS32R6-ALIGNED-NEXT: lw $2, 0($4) 52; MIPS32R6-ALIGNED-NEXT: lw $3, 4($4) 53; MIPS32R6-ALIGNED-NEXT: jrc $ra 54; 55; MIPS64R6-UNALIGNED-LABEL: f1: 56; MIPS64R6-UNALIGNED: # %bb.0: 57; MIPS64R6-UNALIGNED-NEXT: ld $2, 0($4) 58; MIPS64R6-UNALIGNED-NEXT: jrc $ra 59; 60; MIPS64R6-ALIGNED-LABEL: f1: 61; MIPS64R6-ALIGNED: # %bb.0: 62; MIPS64R6-ALIGNED-NEXT: lwu $1, 4($4) 63; MIPS64R6-ALIGNED-NEXT: lwu $2, 0($4) 64; MIPS64R6-ALIGNED-NEXT: dsll $2, $2, 32 65; MIPS64R6-ALIGNED-NEXT: jr $ra 66; MIPS64R6-ALIGNED-NEXT: or $2, $2, $1 67 %tmp = load i64, ptr %p, align 4 68 ret i64 %tmp 69} 70