xref: /llvm-project/llvm/test/CodeGen/Mips/lw16-base-reg.ll (revision cfc1a8787829623ad7427bb7e71f380f6d241262)
1; RUN: llc %s -mtriple=mips -mcpu=mips32r3 -mattr=micromips -filetype=asm \
2; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
3
4; The purpose of this test is to check whether the CodeGen selects
5; LW16 instruction with the base register in a range of $2-$7, $16, $17.
6
7%struct.T = type { i32 }
8
9$_ZN1TaSERKS_ = comdat any
10
11define linkonce_odr void @_ZN1TaSERKS_(ptr %this, ptr dereferenceable(4) %t) #0 comdat align 2 {
12entry:
13  %this.addr = alloca ptr, align 4
14  %t.addr = alloca ptr, align 4
15  %this1 = load ptr, ptr %this.addr, align 4
16  %0 = load ptr, ptr %t.addr, align 4
17  %1 = load i32, ptr %0, align 4
18  store i32 %1, ptr %this1, align 4
19  ret void
20}
21
22; CHECK: lw16 ${{[0-9]+}}, 0(${{[2-7]|16|17}})
23