xref: /llvm-project/llvm/test/CodeGen/Mips/longbranch/long-branch-octeon.ll (revision bcbd60aeb5fe20136fe79270ac1b8f3936883d78)
1;; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2;; Test that Octeon BBIT family of branch can be replaced by
3;; the long branch expansion pass.
4
5; RUN: llc -O3 -mtriple=mips64-octeon-linux -mcpu=octeon -force-mips-long-branch < %s -o - | FileCheck %s
6
7define i64 @bbit1(i64 %a) nounwind {
8; CHECK-LABEL: bbit1:
9; CHECK:       # %bb.0: # %entry
10; CHECK-NEXT:    bbit0 $4, 3, .LBB0_2
11; CHECK-NEXT:    nop
12; CHECK-NEXT:  # %bb.1: # %entry
13; CHECK-NEXT:    j .LBB0_3
14; CHECK-NEXT:    nop
15; CHECK-NEXT:  .LBB0_2: # %endif
16; CHECK-NEXT:    jr $ra
17; CHECK-NEXT:    daddiu $2, $zero, 12
18; CHECK-NEXT:  .LBB0_3: # %if
19; CHECK-NEXT:    jr $ra
20; CHECK-NEXT:    daddiu $2, $zero, 48
21entry:
22  %bit = and i64 %a, 8
23  %res = icmp eq i64 %bit, 0
24  br i1 %res, label %endif, label %if
25if:
26  ret i64 48
27
28endif:
29  ret i64 12
30}
31
32define i64 @bbit132(i64 %a) nounwind {
33; CHECK-LABEL: bbit132:
34; CHECK:       # %bb.0: # %entry
35; CHECK-NEXT:    bbit032 $4, 3, .LBB1_2
36; CHECK-NEXT:    nop
37; CHECK-NEXT:  # %bb.1: # %entry
38; CHECK-NEXT:    j .LBB1_3
39; CHECK-NEXT:    nop
40; CHECK-NEXT:  .LBB1_2: # %endif
41; CHECK-NEXT:    jr $ra
42; CHECK-NEXT:    daddiu $2, $zero, 12
43; CHECK-NEXT:  .LBB1_3: # %if
44; CHECK-NEXT:    jr $ra
45; CHECK-NEXT:    daddiu $2, $zero, 48
46entry:
47  %bit = and i64 %a, 34359738368
48  %res = icmp eq i64 %bit, 0
49  br i1 %res, label %endif, label %if
50if:
51  ret i64 48
52
53endif:
54  ret i64 12
55}
56
57define i64 @bbit0(i64 %a) nounwind {
58; CHECK-LABEL: bbit0:
59; CHECK:       # %bb.0: # %entry
60; CHECK-NEXT:    bbit1 $4, 3, .LBB2_2
61; CHECK-NEXT:    nop
62; CHECK-NEXT:  # %bb.1: # %entry
63; CHECK-NEXT:    j .LBB2_3
64; CHECK-NEXT:    nop
65; CHECK-NEXT:  .LBB2_2: # %endif
66; CHECK-NEXT:    jr $ra
67; CHECK-NEXT:    daddiu $2, $zero, 12
68; CHECK-NEXT:  .LBB2_3: # %if
69; CHECK-NEXT:    jr $ra
70; CHECK-NEXT:    daddiu $2, $zero, 48
71entry:
72  %bit = and i64 %a, 8
73  %res = icmp ne i64 %bit, 0
74  br i1 %res, label %endif, label %if
75if:
76  ret i64 48
77
78endif:
79  ret i64 12
80}
81
82define i64 @bbit032(i64 %a) nounwind {
83; CHECK-LABEL: bbit032:
84; CHECK:       # %bb.0: # %entry
85; CHECK-NEXT:    bbit132 $4, 3, .LBB3_2
86; CHECK-NEXT:    nop
87; CHECK-NEXT:  # %bb.1: # %entry
88; CHECK-NEXT:    j .LBB3_3
89; CHECK-NEXT:    nop
90; CHECK-NEXT:  .LBB3_2: # %endif
91; CHECK-NEXT:    jr $ra
92; CHECK-NEXT:    daddiu $2, $zero, 12
93; CHECK-NEXT:  .LBB3_3: # %if
94; CHECK-NEXT:    jr $ra
95; CHECK-NEXT:    daddiu $2, $zero, 48
96entry:
97  %bit = and i64 %a, 34359738368
98  %res = icmp ne i64 %bit, 0
99  br i1 %res, label %endif, label %if
100if:
101  ret i64 48
102
103endif:
104  ret i64 12
105}
106