1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion | FileCheck %s --check-prefix=R6 3# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion -relocation-model=pic | FileCheck %s --check-prefix=PIC 4 5# Test the long branch expansion of various branches 6 7--- | 8 9 define i32 @a(double %a, double %b) { 10 entry: 11 %cmp = fcmp une double %a, %b 12 br i1 %cmp, label %if.then, label %return 13 14 if.then: ; preds = %entry 15 call void asm sideeffect ".space 310680", "~{$1}"() 16 ret i32 0 17 18 return: ; preds = %entry 19 ret i32 1 20 } 21 22 define i32 @b(double %a, double %b) { 23 entry: 24 %cmp = fcmp ueq double %a, %b 25 br i1 %cmp, label %if.then, label %return 26 27 if.then: ; preds = %entry 28 call void asm sideeffect ".space 310680", "~{$1}"() 29 ret i32 0 30 31 return: ; preds = %entry 32 ret i32 1 33 } 34 35 36... 37--- 38name: a 39alignment: 4 40exposesReturnsTwice: false 41legalized: false 42regBankSelected: false 43selected: false 44failedISel: false 45tracksRegLiveness: true 46registers: 47liveins: 48 - { reg: '$d12_64', virtual-reg: '' } 49 - { reg: '$d14_64', virtual-reg: '' } 50frameInfo: 51 isFrameAddressTaken: false 52 isReturnAddressTaken: false 53 hasStackMap: false 54 hasPatchPoint: false 55 stackSize: 0 56 offsetAdjustment: 0 57 maxAlignment: 1 58 adjustsStack: false 59 hasCalls: false 60 stackProtector: '' 61 maxCallFrameSize: 0 62 hasOpaqueSPAdjustment: false 63 hasVAStart: false 64 hasMustTailInVarArgFunc: false 65 localFrameSize: 0 66 savePoint: '' 67 restorePoint: '' 68fixedStack: 69stack: 70constants: 71body: | 72 ; R6-LABEL: name: a 73 ; R6: bb.0.entry: 74 ; R6: successors: %bb.2(0x50000000), %bb.1(0x30000000) 75 ; R6: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64 76 ; R6: BC1NEZ $d0_64, %bb.2 { 77 ; R6: $zero = SLL $zero, 0 78 ; R6: } 79 ; R6: bb.1.entry: 80 ; R6: successors: %bb.3(0x80000000) 81 ; R6: BC %bb.3 82 ; R6: bb.2.if.then: 83 ; R6: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at 84 ; R6: PseudoReturn undef $ra, implicit killed $v0 { 85 ; R6: $v0 = ADDiu $zero, 0 86 ; R6: } 87 ; R6: bb.3.return: 88 ; R6: PseudoReturn undef $ra, implicit killed $v0 { 89 ; R6: $v0 = ADDiu $zero, 1 90 ; R6: } 91 ; PIC-LABEL: name: a 92 ; PIC: bb.0.entry: 93 ; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000) 94 ; PIC: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64 95 ; PIC: BC1NEZ $d0_64, %bb.3 { 96 ; PIC: $zero = SLL $zero, 0 97 ; PIC: } 98 ; PIC: bb.1.entry: 99 ; PIC: successors: %bb.2(0x80000000) 100 ; PIC: $sp = ADDiu $sp, -8 101 ; PIC: SW $ra, $sp, 0 102 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 103 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 104 ; PIC: BALC %bb.2, implicit-def $ra 105 ; PIC: bb.2.entry: 106 ; PIC: successors: %bb.4(0x80000000) 107 ; PIC: $at = ADDu $ra, $at 108 ; PIC: $ra = LW $sp, 0 109 ; PIC: $sp = ADDiu $sp, 8 110 ; PIC: JIC $at, 0, implicit-def $at 111 ; PIC: bb.3.if.then: 112 ; PIC: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at 113 ; PIC: PseudoReturn undef $ra, implicit killed $v0 { 114 ; PIC: $v0 = ADDiu $zero, 0 115 ; PIC: } 116 ; PIC: bb.4.return: 117 ; PIC: PseudoReturn undef $ra, implicit killed $v0 { 118 ; PIC: $v0 = ADDiu $zero, 1 119 ; PIC: } 120 bb.0.entry: 121 successors: %bb.1(0x50000000), %bb.2(0x30000000) 122 liveins: $d12_64, $d14_64 123 124 $f0 = CMP_EQ_D killed $d12_64, killed $d14_64 125 BC1EQZ killed $d0_64, %bb.2, implicit-def $at 126 127 bb.1.if.then: 128 INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at 129 $v0 = ADDiu $zero, 0 130 PseudoReturn undef $ra, implicit killed $v0 131 132 bb.2.return: 133 $v0 = ADDiu $zero, 1 134 PseudoReturn undef $ra, implicit killed $v0 135 136... 137--- 138name: b 139alignment: 4 140exposesReturnsTwice: false 141legalized: false 142regBankSelected: false 143selected: false 144failedISel: false 145tracksRegLiveness: true 146registers: 147liveins: 148 - { reg: '$d12_64', virtual-reg: '' } 149 - { reg: '$d14_64', virtual-reg: '' } 150frameInfo: 151 isFrameAddressTaken: false 152 isReturnAddressTaken: false 153 hasStackMap: false 154 hasPatchPoint: false 155 stackSize: 0 156 offsetAdjustment: 0 157 maxAlignment: 1 158 adjustsStack: false 159 hasCalls: false 160 stackProtector: '' 161 maxCallFrameSize: 0 162 hasOpaqueSPAdjustment: false 163 hasVAStart: false 164 hasMustTailInVarArgFunc: false 165 localFrameSize: 0 166 savePoint: '' 167 restorePoint: '' 168fixedStack: 169stack: 170constants: 171body: | 172 ; R6-LABEL: name: b 173 ; R6: bb.0.entry: 174 ; R6: successors: %bb.2(0x50000000), %bb.1(0x30000000) 175 ; R6: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64 176 ; R6: BC1EQZ $d0_64, %bb.2 { 177 ; R6: $zero = SLL $zero, 0 178 ; R6: } 179 ; R6: bb.1.entry: 180 ; R6: successors: %bb.3(0x80000000) 181 ; R6: BC %bb.3 182 ; R6: bb.2.if.then: 183 ; R6: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at 184 ; R6: PseudoReturn undef $ra, implicit killed $v0 { 185 ; R6: $v0 = ADDiu $zero, 0 186 ; R6: } 187 ; R6: bb.3.return: 188 ; R6: PseudoReturn undef $ra, implicit killed $v0 { 189 ; R6: $v0 = ADDiu $zero, 1 190 ; R6: } 191 ; PIC-LABEL: name: b 192 ; PIC: bb.0.entry: 193 ; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000) 194 ; PIC: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64 195 ; PIC: BC1EQZ $d0_64, %bb.3 { 196 ; PIC: $zero = SLL $zero, 0 197 ; PIC: } 198 ; PIC: bb.1.entry: 199 ; PIC: successors: %bb.2(0x80000000) 200 ; PIC: $sp = ADDiu $sp, -8 201 ; PIC: SW $ra, $sp, 0 202 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 203 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 204 ; PIC: BALC %bb.2, implicit-def $ra 205 ; PIC: bb.2.entry: 206 ; PIC: successors: %bb.4(0x80000000) 207 ; PIC: $at = ADDu $ra, $at 208 ; PIC: $ra = LW $sp, 0 209 ; PIC: $sp = ADDiu $sp, 8 210 ; PIC: JIC $at, 0, implicit-def $at 211 ; PIC: bb.3.if.then: 212 ; PIC: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at 213 ; PIC: PseudoReturn undef $ra, implicit killed $v0 { 214 ; PIC: $v0 = ADDiu $zero, 0 215 ; PIC: } 216 ; PIC: bb.4.return: 217 ; PIC: PseudoReturn undef $ra, implicit killed $v0 { 218 ; PIC: $v0 = ADDiu $zero, 1 219 ; PIC: } 220 bb.0.entry: 221 successors: %bb.1(0x50000000), %bb.2(0x30000000) 222 liveins: $d12_64, $d14_64 223 224 $f0 = CMP_EQ_D killed $d12_64, killed $d14_64 225 BC1NEZ killed $d0_64, %bb.2, implicit-def $at 226 227 bb.1.if.then: 228 INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at 229 $v0 = ADDiu $zero, 0 230 PseudoReturn undef $ra, implicit killed $v0 231 232 bb.2.return: 233 $v0 = ADDiu $zero, 1 234 PseudoReturn undef $ra, implicit killed $v0 235 236... 237