1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -verify-machineinstrs | FileCheck %s \ 3; RUN: -check-prefixes=M2 4; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -verify-machineinstrs | FileCheck %s \ 5; RUN: -check-prefixes=CMOV32R1 6; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -verify-machineinstrs | FileCheck %s \ 7; RUN: -check-prefixes=CMOV32R2 8; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -verify-machineinstrs | FileCheck %s \ 9; RUN: -check-prefixes=CMOV32R2 10; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -verify-machineinstrs | FileCheck %s \ 11; RUN: -check-prefixes=CMOV32R2 12; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -verify-machineinstrs | FileCheck %s \ 13; RUN: -check-prefixes=32R6 14; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -verify-machineinstrs | FileCheck %s \ 15; RUN: -check-prefixes=M3 16; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -verify-machineinstrs | FileCheck %s \ 17; RUN: -check-prefixes=CMOV64 18; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -verify-machineinstrs | FileCheck %s \ 19; RUN: -check-prefixes=CMOV64 20; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -verify-machineinstrs | FileCheck %s \ 21; RUN: -check-prefixes=CMOV64 22; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -verify-machineinstrs | FileCheck %s \ 23; RUN: -check-prefixes=CMOV64 24; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -verify-machineinstrs | FileCheck %s \ 25; RUN: -check-prefixes=CMOV64 26; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -verify-machineinstrs | FileCheck %s \ 27; RUN: -check-prefixes=64R6 28; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs -asm-show-inst | FileCheck %s \ 29; RUN: -check-prefixes=MM32R3 30; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs | FileCheck %s \ 31; RUN: -check-prefixes=MM32R6 32 33define float @tst_select_i1_float(i1 signext %s, float %x, float %y) { 34; M2-LABEL: tst_select_i1_float: 35; M2: # %bb.0: # %entry 36; M2-NEXT: andi $1, $4, 1 37; M2-NEXT: bnez $1, $BB0_2 38; M2-NEXT: nop 39; M2-NEXT: # %bb.1: # %entry 40; M2-NEXT: jr $ra 41; M2-NEXT: mtc1 $6, $f0 42; M2-NEXT: $BB0_2: 43; M2-NEXT: jr $ra 44; M2-NEXT: mtc1 $5, $f0 45; 46; CMOV32R1-LABEL: tst_select_i1_float: 47; CMOV32R1: # %bb.0: # %entry 48; CMOV32R1-NEXT: mtc1 $6, $f0 49; CMOV32R1-NEXT: andi $1, $4, 1 50; CMOV32R1-NEXT: mtc1 $5, $f1 51; CMOV32R1-NEXT: jr $ra 52; CMOV32R1-NEXT: movn.s $f0, $f1, $1 53; 54; CMOV32R2-LABEL: tst_select_i1_float: 55; CMOV32R2: # %bb.0: # %entry 56; CMOV32R2-NEXT: mtc1 $6, $f0 57; CMOV32R2-NEXT: andi $1, $4, 1 58; CMOV32R2-NEXT: mtc1 $5, $f1 59; CMOV32R2-NEXT: jr $ra 60; CMOV32R2-NEXT: movn.s $f0, $f1, $1 61; 62; 32R6-LABEL: tst_select_i1_float: 63; 32R6: # %bb.0: # %entry 64; 32R6-NEXT: mtc1 $5, $f1 65; 32R6-NEXT: mtc1 $6, $f2 66; 32R6-NEXT: mtc1 $4, $f0 67; 32R6-NEXT: jr $ra 68; 32R6-NEXT: sel.s $f0, $f2, $f1 69; 70; M3-LABEL: tst_select_i1_float: 71; M3: # %bb.0: # %entry 72; M3-NEXT: andi $1, $4, 1 73; M3-NEXT: bnez $1, .LBB0_2 74; M3-NEXT: mov.s $f0, $f13 75; M3-NEXT: # %bb.1: # %entry 76; M3-NEXT: mov.s $f0, $f14 77; M3-NEXT: .LBB0_2: # %entry 78; M3-NEXT: jr $ra 79; M3-NEXT: nop 80; 81; CMOV64-LABEL: tst_select_i1_float: 82; CMOV64: # %bb.0: # %entry 83; CMOV64-NEXT: mov.s $f0, $f14 84; CMOV64-NEXT: andi $1, $4, 1 85; CMOV64-NEXT: jr $ra 86; CMOV64-NEXT: movn.s $f0, $f13, $1 87; 88; 64R6-LABEL: tst_select_i1_float: 89; 64R6: # %bb.0: # %entry 90; 64R6-NEXT: mtc1 $4, $f0 91; 64R6-NEXT: jr $ra 92; 64R6-NEXT: sel.s $f0, $f14, $f13 93; 94; MM32R3-LABEL: tst_select_i1_float: 95; MM32R3: # %bb.0: # %entry 96; MM32R3: mtc1 $6, $f0 # <MCInst #{{.*}} MTC1_MM 97; MM32R3: andi16 $2, $4, 1 # <MCInst #{{.*}} ANDI16_MM 98; MM32R3: mtc1 $5, $f1 # <MCInst #{{.*}} MTC1_MM 99; MM32R3: jr $ra # <MCInst #{{.*}} JR_MM 100; MM32R3: movn.s $f0, $f1, $2 # <MCInst #{{.*}} MOVN_I_S_MM 101; 102; MM32R6-LABEL: tst_select_i1_float: 103; MM32R6: # %bb.0: # %entry 104; MM32R6-NEXT: mtc1 $5, $f1 105; MM32R6-NEXT: mtc1 $6, $f2 106; MM32R6-NEXT: mtc1 $4, $f0 107; MM32R6-NEXT: sel.s $f0, $f2, $f1 108; MM32R6-NEXT: jrc $ra 109entry: 110 %r = select i1 %s, float %x, float %y 111 ret float %r 112} 113 114define float @tst_select_i1_float_reordered(float %x, float %y, 115; M2-LABEL: tst_select_i1_float_reordered: 116; M2: # %bb.0: # %entry 117; M2-NEXT: andi $1, $6, 1 118; M2-NEXT: bnez $1, $BB1_2 119; M2-NEXT: mov.s $f0, $f12 120; M2-NEXT: # %bb.1: # %entry 121; M2-NEXT: mov.s $f0, $f14 122; M2-NEXT: $BB1_2: # %entry 123; M2-NEXT: jr $ra 124; M2-NEXT: nop 125; 126; CMOV32R1-LABEL: tst_select_i1_float_reordered: 127; CMOV32R1: # %bb.0: # %entry 128; CMOV32R1-NEXT: mov.s $f0, $f14 129; CMOV32R1-NEXT: andi $1, $6, 1 130; CMOV32R1-NEXT: jr $ra 131; CMOV32R1-NEXT: movn.s $f0, $f12, $1 132; 133; CMOV32R2-LABEL: tst_select_i1_float_reordered: 134; CMOV32R2: # %bb.0: # %entry 135; CMOV32R2-NEXT: mov.s $f0, $f14 136; CMOV32R2-NEXT: andi $1, $6, 1 137; CMOV32R2-NEXT: jr $ra 138; CMOV32R2-NEXT: movn.s $f0, $f12, $1 139; 140; 32R6-LABEL: tst_select_i1_float_reordered: 141; 32R6: # %bb.0: # %entry 142; 32R6-NEXT: mtc1 $6, $f0 143; 32R6-NEXT: jr $ra 144; 32R6-NEXT: sel.s $f0, $f14, $f12 145; 146; M3-LABEL: tst_select_i1_float_reordered: 147; M3: # %bb.0: # %entry 148; M3-NEXT: andi $1, $6, 1 149; M3-NEXT: bnez $1, .LBB1_2 150; M3-NEXT: mov.s $f0, $f12 151; M3-NEXT: # %bb.1: # %entry 152; M3-NEXT: mov.s $f0, $f13 153; M3-NEXT: .LBB1_2: # %entry 154; M3-NEXT: jr $ra 155; M3-NEXT: nop 156; 157; CMOV64-LABEL: tst_select_i1_float_reordered: 158; CMOV64: # %bb.0: # %entry 159; CMOV64-NEXT: mov.s $f0, $f13 160; CMOV64-NEXT: andi $1, $6, 1 161; CMOV64-NEXT: jr $ra 162; CMOV64-NEXT: movn.s $f0, $f12, $1 163; 164; 64R6-LABEL: tst_select_i1_float_reordered: 165; 64R6: # %bb.0: # %entry 166; 64R6-NEXT: mtc1 $6, $f0 167; 64R6-NEXT: jr $ra 168; 64R6-NEXT: sel.s $f0, $f13, $f12 169; 170; MM32R3-LABEL: tst_select_i1_float_reordered: 171; MM32R3: # %bb.0: # %entry 172; MM32R3: mov.s $f0, $f14 # <MCInst #{{.*}} FMOV_S 173; MM32R3: andi16 $2, $6, 1 # <MCInst #{{.*}} ANDI16_MM 174; MM32R3: jr $ra # <MCInst #{{.*}} JR_MM 175; MM32R3: movn.s $f0, $f12, $2 # <MCInst #{{.*}} MOVN_I_S_MM 176; 177; MM32R6-LABEL: tst_select_i1_float_reordered: 178; MM32R6: # %bb.0: # %entry 179; MM32R6-NEXT: mtc1 $6, $f0 180; MM32R6-NEXT: sel.s $f0, $f14, $f12 181; MM32R6-NEXT: jrc $ra 182 i1 signext %s) { 183entry: 184 %r = select i1 %s, float %x, float %y 185 ret float %r 186} 187 188define float @tst_select_fcmp_olt_float(float %x, float %y) { 189; M2-LABEL: tst_select_fcmp_olt_float: 190; M2: # %bb.0: # %entry 191; M2-NEXT: c.olt.s $f12, $f14 192; M2-NEXT: nop 193; M2-NEXT: bc1t $BB2_2 194; M2-NEXT: mov.s $f0, $f12 195; M2-NEXT: # %bb.1: # %entry 196; M2-NEXT: mov.s $f0, $f14 197; M2-NEXT: $BB2_2: # %entry 198; M2-NEXT: jr $ra 199; M2-NEXT: nop 200; 201; CMOV32R1-LABEL: tst_select_fcmp_olt_float: 202; CMOV32R1: # %bb.0: # %entry 203; CMOV32R1-NEXT: mov.s $f0, $f14 204; CMOV32R1-NEXT: c.olt.s $f12, $f14 205; CMOV32R1-NEXT: jr $ra 206; CMOV32R1-NEXT: movt.s $f0, $f12, $fcc0 207; 208; CMOV32R2-LABEL: tst_select_fcmp_olt_float: 209; CMOV32R2: # %bb.0: # %entry 210; CMOV32R2-NEXT: mov.s $f0, $f14 211; CMOV32R2-NEXT: c.olt.s $f12, $f14 212; CMOV32R2-NEXT: jr $ra 213; CMOV32R2-NEXT: movt.s $f0, $f12, $fcc0 214; 215; 32R6-LABEL: tst_select_fcmp_olt_float: 216; 32R6: # %bb.0: # %entry 217; 32R6-NEXT: cmp.lt.s $f0, $f12, $f14 218; 32R6-NEXT: jr $ra 219; 32R6-NEXT: sel.s $f0, $f14, $f12 220; 221; M3-LABEL: tst_select_fcmp_olt_float: 222; M3: # %bb.0: # %entry 223; M3-NEXT: c.olt.s $f12, $f13 224; M3-NEXT: nop 225; M3-NEXT: bc1t .LBB2_2 226; M3-NEXT: mov.s $f0, $f12 227; M3-NEXT: # %bb.1: # %entry 228; M3-NEXT: mov.s $f0, $f13 229; M3-NEXT: .LBB2_2: # %entry 230; M3-NEXT: jr $ra 231; M3-NEXT: nop 232; 233; CMOV64-LABEL: tst_select_fcmp_olt_float: 234; CMOV64: # %bb.0: # %entry 235; CMOV64-NEXT: mov.s $f0, $f13 236; CMOV64-NEXT: c.olt.s $f12, $f13 237; CMOV64-NEXT: jr $ra 238; CMOV64-NEXT: movt.s $f0, $f12, $fcc0 239; 240; 64R6-LABEL: tst_select_fcmp_olt_float: 241; 64R6: # %bb.0: # %entry 242; 64R6-NEXT: cmp.lt.s $f0, $f12, $f13 243; 64R6-NEXT: jr $ra 244; 64R6-NEXT: sel.s $f0, $f13, $f12 245; 246; MM32R3-LABEL: tst_select_fcmp_olt_float: 247; MM32R3: # %bb.0: # %entry 248; MM32R3: mov.s $f0, $f14 # <MCInst #{{.*}} FMOV_S 249; MM32R3: c.olt.s $f12, $f14 # <MCInst #{{.*}} FCMP_S32_MM 250; MM32R3: jr $ra # <MCInst #{{.*}} JR_MM 251; MM32R3: movt.s $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVT_S_MM 252; 253; MM32R6-LABEL: tst_select_fcmp_olt_float: 254; MM32R6: # %bb.0: # %entry 255; MM32R6-NEXT: cmp.lt.s $f0, $f12, $f14 256; MM32R6-NEXT: sel.s $f0, $f14, $f12 257; MM32R6-NEXT: jrc $ra 258entry: 259 %s = fcmp olt float %x, %y 260 %r = select i1 %s, float %x, float %y 261 ret float %r 262} 263 264define float @tst_select_fcmp_ole_float(float %x, float %y) { 265; M2-LABEL: tst_select_fcmp_ole_float: 266; M2: # %bb.0: # %entry 267; M2-NEXT: c.ole.s $f12, $f14 268; M2-NEXT: nop 269; M2-NEXT: bc1t $BB3_2 270; M2-NEXT: mov.s $f0, $f12 271; M2-NEXT: # %bb.1: # %entry 272; M2-NEXT: mov.s $f0, $f14 273; M2-NEXT: $BB3_2: # %entry 274; M2-NEXT: jr $ra 275; M2-NEXT: nop 276; 277; CMOV32R1-LABEL: tst_select_fcmp_ole_float: 278; CMOV32R1: # %bb.0: # %entry 279; CMOV32R1-NEXT: mov.s $f0, $f14 280; CMOV32R1-NEXT: c.ole.s $f12, $f14 281; CMOV32R1-NEXT: jr $ra 282; CMOV32R1-NEXT: movt.s $f0, $f12, $fcc0 283; 284; CMOV32R2-LABEL: tst_select_fcmp_ole_float: 285; CMOV32R2: # %bb.0: # %entry 286; CMOV32R2-NEXT: mov.s $f0, $f14 287; CMOV32R2-NEXT: c.ole.s $f12, $f14 288; CMOV32R2-NEXT: jr $ra 289; CMOV32R2-NEXT: movt.s $f0, $f12, $fcc0 290; 291; 32R6-LABEL: tst_select_fcmp_ole_float: 292; 32R6: # %bb.0: # %entry 293; 32R6-NEXT: cmp.le.s $f0, $f12, $f14 294; 32R6-NEXT: jr $ra 295; 32R6-NEXT: sel.s $f0, $f14, $f12 296; 297; M3-LABEL: tst_select_fcmp_ole_float: 298; M3: # %bb.0: # %entry 299; M3-NEXT: c.ole.s $f12, $f13 300; M3-NEXT: nop 301; M3-NEXT: bc1t .LBB3_2 302; M3-NEXT: mov.s $f0, $f12 303; M3-NEXT: # %bb.1: # %entry 304; M3-NEXT: mov.s $f0, $f13 305; M3-NEXT: .LBB3_2: # %entry 306; M3-NEXT: jr $ra 307; M3-NEXT: nop 308; 309; CMOV64-LABEL: tst_select_fcmp_ole_float: 310; CMOV64: # %bb.0: # %entry 311; CMOV64-NEXT: mov.s $f0, $f13 312; CMOV64-NEXT: c.ole.s $f12, $f13 313; CMOV64-NEXT: jr $ra 314; CMOV64-NEXT: movt.s $f0, $f12, $fcc0 315; 316; 64R6-LABEL: tst_select_fcmp_ole_float: 317; 64R6: # %bb.0: # %entry 318; 64R6-NEXT: cmp.le.s $f0, $f12, $f13 319; 64R6-NEXT: jr $ra 320; 64R6-NEXT: sel.s $f0, $f13, $f12 321; 322; MM32R3-LABEL: tst_select_fcmp_ole_float: 323; MM32R3: # %bb.0: # %entry 324; MM32R3: mov.s $f0, $f14 # <MCInst #{{.*}} FMOV_S 325; MM32R3: c.ole.s $f12, $f14 # <MCInst #{{.*}} FCMP_S32_MM 326; MM32R3: jr $ra # <MCInst #{{.*}} JR_MM 327; MM32R3: movt.s $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVT_S_MM 328; 329; MM32R6-LABEL: tst_select_fcmp_ole_float: 330; MM32R6: # %bb.0: # %entry 331; MM32R6-NEXT: cmp.le.s $f0, $f12, $f14 332; MM32R6-NEXT: sel.s $f0, $f14, $f12 333; MM32R6-NEXT: jrc $ra 334entry: 335 %s = fcmp ole float %x, %y 336 %r = select i1 %s, float %x, float %y 337 ret float %r 338} 339 340define float @tst_select_fcmp_ogt_float(float %x, float %y) { 341; M2-LABEL: tst_select_fcmp_ogt_float: 342; M2: # %bb.0: # %entry 343; M2-NEXT: c.ule.s $f12, $f14 344; M2-NEXT: nop 345; M2-NEXT: bc1f $BB4_2 346; M2-NEXT: mov.s $f0, $f12 347; M2-NEXT: # %bb.1: # %entry 348; M2-NEXT: mov.s $f0, $f14 349; M2-NEXT: $BB4_2: # %entry 350; M2-NEXT: jr $ra 351; M2-NEXT: nop 352; 353; CMOV32R1-LABEL: tst_select_fcmp_ogt_float: 354; CMOV32R1: # %bb.0: # %entry 355; CMOV32R1-NEXT: mov.s $f0, $f14 356; CMOV32R1-NEXT: c.ule.s $f12, $f14 357; CMOV32R1-NEXT: jr $ra 358; CMOV32R1-NEXT: movf.s $f0, $f12, $fcc0 359; 360; CMOV32R2-LABEL: tst_select_fcmp_ogt_float: 361; CMOV32R2: # %bb.0: # %entry 362; CMOV32R2-NEXT: mov.s $f0, $f14 363; CMOV32R2-NEXT: c.ule.s $f12, $f14 364; CMOV32R2-NEXT: jr $ra 365; CMOV32R2-NEXT: movf.s $f0, $f12, $fcc0 366; 367; 32R6-LABEL: tst_select_fcmp_ogt_float: 368; 32R6: # %bb.0: # %entry 369; 32R6-NEXT: cmp.lt.s $f0, $f14, $f12 370; 32R6-NEXT: jr $ra 371; 32R6-NEXT: sel.s $f0, $f14, $f12 372; 373; M3-LABEL: tst_select_fcmp_ogt_float: 374; M3: # %bb.0: # %entry 375; M3-NEXT: c.ule.s $f12, $f13 376; M3-NEXT: nop 377; M3-NEXT: bc1f .LBB4_2 378; M3-NEXT: mov.s $f0, $f12 379; M3-NEXT: # %bb.1: # %entry 380; M3-NEXT: mov.s $f0, $f13 381; M3-NEXT: .LBB4_2: # %entry 382; M3-NEXT: jr $ra 383; M3-NEXT: nop 384; 385; CMOV64-LABEL: tst_select_fcmp_ogt_float: 386; CMOV64: # %bb.0: # %entry 387; CMOV64-NEXT: mov.s $f0, $f13 388; CMOV64-NEXT: c.ule.s $f12, $f13 389; CMOV64-NEXT: jr $ra 390; CMOV64-NEXT: movf.s $f0, $f12, $fcc0 391; 392; 64R6-LABEL: tst_select_fcmp_ogt_float: 393; 64R6: # %bb.0: # %entry 394; 64R6-NEXT: cmp.lt.s $f0, $f13, $f12 395; 64R6-NEXT: jr $ra 396; 64R6-NEXT: sel.s $f0, $f13, $f12 397; 398; MM32R3-LABEL: tst_select_fcmp_ogt_float: 399; MM32R3: # %bb.0: # %entry 400; MM32R3: mov.s $f0, $f14 # <MCInst #{{.*}} FMOV_S 401; MM32R3: c.ule.s $f12, $f14 # <MCInst #{{.*}} FCMP_S32_MM 402; MM32R3: jr $ra # <MCInst #{{.*}} JR_MM 403; MM32R3: movf.s $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVF_S_MM 404; 405; MM32R6-LABEL: tst_select_fcmp_ogt_float: 406; MM32R6: # %bb.0: # %entry 407; MM32R6-NEXT: cmp.lt.s $f0, $f14, $f12 408; MM32R6-NEXT: sel.s $f0, $f14, $f12 409; MM32R6-NEXT: jrc $ra 410entry: 411 %s = fcmp ogt float %x, %y 412 %r = select i1 %s, float %x, float %y 413 ret float %r 414} 415 416define float @tst_select_fcmp_oge_float(float %x, float %y) { 417; M2-LABEL: tst_select_fcmp_oge_float: 418; M2: # %bb.0: # %entry 419; M2-NEXT: c.ult.s $f12, $f14 420; M2-NEXT: nop 421; M2-NEXT: bc1f $BB5_2 422; M2-NEXT: mov.s $f0, $f12 423; M2-NEXT: # %bb.1: # %entry 424; M2-NEXT: mov.s $f0, $f14 425; M2-NEXT: $BB5_2: # %entry 426; M2-NEXT: jr $ra 427; M2-NEXT: nop 428; 429; CMOV32R1-LABEL: tst_select_fcmp_oge_float: 430; CMOV32R1: # %bb.0: # %entry 431; CMOV32R1-NEXT: mov.s $f0, $f14 432; CMOV32R1-NEXT: c.ult.s $f12, $f14 433; CMOV32R1-NEXT: jr $ra 434; CMOV32R1-NEXT: movf.s $f0, $f12, $fcc0 435; 436; CMOV32R2-LABEL: tst_select_fcmp_oge_float: 437; CMOV32R2: # %bb.0: # %entry 438; CMOV32R2-NEXT: mov.s $f0, $f14 439; CMOV32R2-NEXT: c.ult.s $f12, $f14 440; CMOV32R2-NEXT: jr $ra 441; CMOV32R2-NEXT: movf.s $f0, $f12, $fcc0 442; 443; 32R6-LABEL: tst_select_fcmp_oge_float: 444; 32R6: # %bb.0: # %entry 445; 32R6-NEXT: cmp.le.s $f0, $f14, $f12 446; 32R6-NEXT: jr $ra 447; 32R6-NEXT: sel.s $f0, $f14, $f12 448; 449; M3-LABEL: tst_select_fcmp_oge_float: 450; M3: # %bb.0: # %entry 451; M3-NEXT: c.ult.s $f12, $f13 452; M3-NEXT: nop 453; M3-NEXT: bc1f .LBB5_2 454; M3-NEXT: mov.s $f0, $f12 455; M3-NEXT: # %bb.1: # %entry 456; M3-NEXT: mov.s $f0, $f13 457; M3-NEXT: .LBB5_2: # %entry 458; M3-NEXT: jr $ra 459; M3-NEXT: nop 460; 461; CMOV64-LABEL: tst_select_fcmp_oge_float: 462; CMOV64: # %bb.0: # %entry 463; CMOV64-NEXT: mov.s $f0, $f13 464; CMOV64-NEXT: c.ult.s $f12, $f13 465; CMOV64-NEXT: jr $ra 466; CMOV64-NEXT: movf.s $f0, $f12, $fcc0 467; 468; 64R6-LABEL: tst_select_fcmp_oge_float: 469; 64R6: # %bb.0: # %entry 470; 64R6-NEXT: cmp.le.s $f0, $f13, $f12 471; 64R6-NEXT: jr $ra 472; 64R6-NEXT: sel.s $f0, $f13, $f12 473; 474; MM32R3-LABEL: tst_select_fcmp_oge_float: 475; MM32R3: # %bb.0: # %entry 476; MM32R3: mov.s $f0, $f14 # <MCInst #{{.*}} FMOV_S 477; MM32R3: c.ult.s $f12, $f14 # <MCInst #{{.*}} FCMP_S32_MM 478; MM32R3: jr $ra # <MCInst #{{.*}} JR_MM 479; MM32R3: movf.s $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVF_S_MM 480; 481; MM32R6-LABEL: tst_select_fcmp_oge_float: 482; MM32R6: # %bb.0: # %entry 483; MM32R6-NEXT: cmp.le.s $f0, $f14, $f12 484; MM32R6-NEXT: sel.s $f0, $f14, $f12 485; MM32R6-NEXT: jrc $ra 486entry: 487 %s = fcmp oge float %x, %y 488 %r = select i1 %s, float %x, float %y 489 ret float %r 490} 491 492define float @tst_select_fcmp_oeq_float(float %x, float %y) { 493; M2-LABEL: tst_select_fcmp_oeq_float: 494; M2: # %bb.0: # %entry 495; M2-NEXT: c.eq.s $f12, $f14 496; M2-NEXT: nop 497; M2-NEXT: bc1t $BB6_2 498; M2-NEXT: mov.s $f0, $f12 499; M2-NEXT: # %bb.1: # %entry 500; M2-NEXT: mov.s $f0, $f14 501; M2-NEXT: $BB6_2: # %entry 502; M2-NEXT: jr $ra 503; M2-NEXT: nop 504; 505; CMOV32R1-LABEL: tst_select_fcmp_oeq_float: 506; CMOV32R1: # %bb.0: # %entry 507; CMOV32R1-NEXT: mov.s $f0, $f14 508; CMOV32R1-NEXT: c.eq.s $f12, $f14 509; CMOV32R1-NEXT: jr $ra 510; CMOV32R1-NEXT: movt.s $f0, $f12, $fcc0 511; 512; CMOV32R2-LABEL: tst_select_fcmp_oeq_float: 513; CMOV32R2: # %bb.0: # %entry 514; CMOV32R2-NEXT: mov.s $f0, $f14 515; CMOV32R2-NEXT: c.eq.s $f12, $f14 516; CMOV32R2-NEXT: jr $ra 517; CMOV32R2-NEXT: movt.s $f0, $f12, $fcc0 518; 519; 32R6-LABEL: tst_select_fcmp_oeq_float: 520; 32R6: # %bb.0: # %entry 521; 32R6-NEXT: cmp.eq.s $f0, $f12, $f14 522; 32R6-NEXT: jr $ra 523; 32R6-NEXT: sel.s $f0, $f14, $f12 524; 525; M3-LABEL: tst_select_fcmp_oeq_float: 526; M3: # %bb.0: # %entry 527; M3-NEXT: c.eq.s $f12, $f13 528; M3-NEXT: nop 529; M3-NEXT: bc1t .LBB6_2 530; M3-NEXT: mov.s $f0, $f12 531; M3-NEXT: # %bb.1: # %entry 532; M3-NEXT: mov.s $f0, $f13 533; M3-NEXT: .LBB6_2: # %entry 534; M3-NEXT: jr $ra 535; M3-NEXT: nop 536; 537; CMOV64-LABEL: tst_select_fcmp_oeq_float: 538; CMOV64: # %bb.0: # %entry 539; CMOV64-NEXT: mov.s $f0, $f13 540; CMOV64-NEXT: c.eq.s $f12, $f13 541; CMOV64-NEXT: jr $ra 542; CMOV64-NEXT: movt.s $f0, $f12, $fcc0 543; 544; 64R6-LABEL: tst_select_fcmp_oeq_float: 545; 64R6: # %bb.0: # %entry 546; 64R6-NEXT: cmp.eq.s $f0, $f12, $f13 547; 64R6-NEXT: jr $ra 548; 64R6-NEXT: sel.s $f0, $f13, $f12 549; 550; MM32R3-LABEL: tst_select_fcmp_oeq_float: 551; MM32R3: # %bb.0: # %entry 552; MM32R3: mov.s $f0, $f14 # <MCInst #{{.*}} FMOV_S 553; MM32R3: c.eq.s $f12, $f14 # <MCInst #{{.*}} FCMP_S32_MM 554; MM32R3: jr $ra # <MCInst #{{.*}} JR_MM 555; MM32R3: movt.s $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVT_S_MM 556; 557; MM32R6-LABEL: tst_select_fcmp_oeq_float: 558; MM32R6: # %bb.0: # %entry 559; MM32R6-NEXT: cmp.eq.s $f0, $f12, $f14 560; MM32R6-NEXT: sel.s $f0, $f14, $f12 561; MM32R6-NEXT: jrc $ra 562entry: 563 %s = fcmp oeq float %x, %y 564 %r = select i1 %s, float %x, float %y 565 ret float %r 566} 567 568define float @tst_select_fcmp_one_float(float %x, float %y) { 569; M2-LABEL: tst_select_fcmp_one_float: 570; M2: # %bb.0: # %entry 571; M2-NEXT: c.ueq.s $f12, $f14 572; M2-NEXT: nop 573; M2-NEXT: bc1f $BB7_2 574; M2-NEXT: mov.s $f0, $f12 575; M2-NEXT: # %bb.1: # %entry 576; M2-NEXT: mov.s $f0, $f14 577; M2-NEXT: $BB7_2: # %entry 578; M2-NEXT: jr $ra 579; M2-NEXT: nop 580; 581; CMOV32R1-LABEL: tst_select_fcmp_one_float: 582; CMOV32R1: # %bb.0: # %entry 583; CMOV32R1-NEXT: mov.s $f0, $f14 584; CMOV32R1-NEXT: c.ueq.s $f12, $f14 585; CMOV32R1-NEXT: jr $ra 586; CMOV32R1-NEXT: movf.s $f0, $f12, $fcc0 587; 588; CMOV32R2-LABEL: tst_select_fcmp_one_float: 589; CMOV32R2: # %bb.0: # %entry 590; CMOV32R2-NEXT: mov.s $f0, $f14 591; CMOV32R2-NEXT: c.ueq.s $f12, $f14 592; CMOV32R2-NEXT: jr $ra 593; CMOV32R2-NEXT: movf.s $f0, $f12, $fcc0 594; 595; 32R6-LABEL: tst_select_fcmp_one_float: 596; 32R6: # %bb.0: # %entry 597; 32R6-NEXT: cmp.ueq.s $f0, $f12, $f14 598; 32R6-NEXT: mfc1 $1, $f0 599; 32R6-NEXT: not $1, $1 600; 32R6-NEXT: mtc1 $1, $f0 601; 32R6-NEXT: jr $ra 602; 32R6-NEXT: sel.s $f0, $f14, $f12 603; 604; M3-LABEL: tst_select_fcmp_one_float: 605; M3: # %bb.0: # %entry 606; M3-NEXT: c.ueq.s $f12, $f13 607; M3-NEXT: nop 608; M3-NEXT: bc1f .LBB7_2 609; M3-NEXT: mov.s $f0, $f12 610; M3-NEXT: # %bb.1: # %entry 611; M3-NEXT: mov.s $f0, $f13 612; M3-NEXT: .LBB7_2: # %entry 613; M3-NEXT: jr $ra 614; M3-NEXT: nop 615; 616; CMOV64-LABEL: tst_select_fcmp_one_float: 617; CMOV64: # %bb.0: # %entry 618; CMOV64-NEXT: mov.s $f0, $f13 619; CMOV64-NEXT: c.ueq.s $f12, $f13 620; CMOV64-NEXT: jr $ra 621; CMOV64-NEXT: movf.s $f0, $f12, $fcc0 622; 623; 64R6-LABEL: tst_select_fcmp_one_float: 624; 64R6: # %bb.0: # %entry 625; 64R6-NEXT: cmp.ueq.s $f0, $f12, $f13 626; 64R6-NEXT: mfc1 $1, $f0 627; 64R6-NEXT: not $1, $1 628; 64R6-NEXT: mtc1 $1, $f0 629; 64R6-NEXT: jr $ra 630; 64R6-NEXT: sel.s $f0, $f13, $f12 631; 632; MM32R3-LABEL: tst_select_fcmp_one_float: 633; MM32R3: # %bb.0: # %entry 634; MM32R3: mov.s $f0, $f14 # <MCInst #{{.*}} FMOV_S 635; MM32R3: c.ueq.s $f12, $f14 # <MCInst #{{.*}} FCMP_S32_MM 636; MM32R3: jr $ra # <MCInst #{{.*}} JR_MM 637; MM32R3: movf.s $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVF_S_MM 638; 639; MM32R6-LABEL: tst_select_fcmp_one_float: 640; MM32R6: # %bb.0: # %entry 641; MM32R6-NEXT: cmp.ueq.s $f0, $f12, $f14 642; MM32R6-NEXT: mfc1 $1, $f0 643; MM32R6-NEXT: not $1, $1 644; MM32R6-NEXT: mtc1 $1, $f0 645; MM32R6-NEXT: sel.s $f0, $f14, $f12 646; MM32R6-NEXT: jrc $ra 647entry: 648 %s = fcmp one float %x, %y 649 %r = select i1 %s, float %x, float %y 650 ret float %r 651} 652