xref: /llvm-project/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll (revision f0f6bba5b285632577fd77aa802b07d927f2573e) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -verify-machineinstrs | FileCheck %s \
3; RUN:    -check-prefix=M2
4; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -verify-machineinstrs | FileCheck %s \
5; RUN:    -check-prefix=CMOV32R1
6; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -verify-machineinstrs | FileCheck %s \
7; RUN:    -check-prefix=CMOV32R2
8; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -verify-machineinstrs | FileCheck %s \
9; RUN:    -check-prefix=CMOV32R2
10; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -verify-machineinstrs | FileCheck %s \
11; RUN:    -check-prefix=CMOV32R2
12; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -verify-machineinstrs | FileCheck %s \
13; RUN:    -check-prefix=32R6
14; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -verify-machineinstrs | FileCheck %s \
15; RUN:    -check-prefix=M3
16; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -verify-machineinstrs | FileCheck %s \
17; RUN:    -check-prefix=CMOV64
18; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -verify-machineinstrs | FileCheck %s \
19; RUN:    -check-prefix=CMOV64
20; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -verify-machineinstrs | FileCheck %s \
21; RUN:    -check-prefix=CMOV64
22; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -verify-machineinstrs | FileCheck %s \
23; RUN:    -check-prefix=CMOV64
24; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -verify-machineinstrs | FileCheck %s \
25; RUN:    -check-prefix=CMOV64
26; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -verify-machineinstrs | FileCheck %s \
27; RUN:    -check-prefix=64R6
28; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 \
29; RUN:   -asm-show-inst -mattr=+micromips -verify-machineinstrs | FileCheck %s \
30; RUN:    -check-prefix=MM32R3
31; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
32; RUN:    -check-prefix=MM32R6
33
34define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
35; M2-LABEL: tst_select_i1_double:
36; M2:       # %bb.0: # %entry
37; M2-NEXT:    andi $1, $4, 1
38; M2-NEXT:    bnez $1, $BB0_2
39; M2-NEXT:    nop
40; M2-NEXT:  # %bb.1: # %entry
41; M2-NEXT:    ldc1 $f0, 16($sp)
42; M2-NEXT:    jr $ra
43; M2-NEXT:    nop
44; M2-NEXT:  $BB0_2:
45; M2-NEXT:    mtc1 $7, $f0
46; M2-NEXT:    jr $ra
47; M2-NEXT:    mtc1 $6, $f1
48;
49; CMOV32R1-LABEL: tst_select_i1_double:
50; CMOV32R1:       # %bb.0: # %entry
51; CMOV32R1-NEXT:    mtc1 $7, $f2
52; CMOV32R1-NEXT:    mtc1 $6, $f3
53; CMOV32R1-NEXT:    andi $1, $4, 1
54; CMOV32R1-NEXT:    ldc1 $f0, 16($sp)
55; CMOV32R1-NEXT:    jr $ra
56; CMOV32R1-NEXT:    movn.d $f0, $f2, $1
57;
58; CMOV32R2-LABEL: tst_select_i1_double:
59; CMOV32R2:       # %bb.0: # %entry
60; CMOV32R2-NEXT:    mtc1 $7, $f2
61; CMOV32R2-NEXT:    mthc1 $6, $f2
62; CMOV32R2-NEXT:    andi $1, $4, 1
63; CMOV32R2-NEXT:    ldc1 $f0, 16($sp)
64; CMOV32R2-NEXT:    jr $ra
65; CMOV32R2-NEXT:    movn.d $f0, $f2, $1
66;
67; 32R6-LABEL: tst_select_i1_double:
68; 32R6:       # %bb.0: # %entry
69; 32R6-NEXT:    mtc1 $7, $f1
70; 32R6-NEXT:    mthc1 $6, $f1
71; 32R6-NEXT:    mtc1 $4, $f0
72; 32R6-NEXT:    ldc1 $f2, 16($sp)
73; 32R6-NEXT:    jr $ra
74; 32R6-NEXT:    sel.d $f0, $f2, $f1
75;
76; M3-LABEL: tst_select_i1_double:
77; M3:       # %bb.0: # %entry
78; M3-NEXT:    andi $1, $4, 1
79; M3-NEXT:    bnez $1, .LBB0_2
80; M3-NEXT:    mov.d $f0, $f13
81; M3-NEXT:  # %bb.1: # %entry
82; M3-NEXT:    mov.d $f0, $f14
83; M3-NEXT:  .LBB0_2: # %entry
84; M3-NEXT:    jr $ra
85; M3-NEXT:    nop
86;
87; CMOV64-LABEL: tst_select_i1_double:
88; CMOV64:       # %bb.0: # %entry
89; CMOV64-NEXT:    mov.d $f0, $f14
90; CMOV64-NEXT:    andi $1, $4, 1
91; CMOV64-NEXT:    jr $ra
92; CMOV64-NEXT:    movn.d $f0, $f13, $1
93;
94; 64R6-LABEL: tst_select_i1_double:
95; 64R6:       # %bb.0: # %entry
96; 64R6-NEXT:    mtc1 $4, $f0
97; 64R6-NEXT:    jr $ra
98; 64R6-NEXT:    sel.d $f0, $f14, $f13
99;
100; MM32R3-LABEL: tst_select_i1_double:
101; MM32R3:       # %bb.0: # %entry
102; MM32R3:       mtc1 $7, $f2 # <MCInst #{{.*}} MTC1
103; MM32R3:       mthc1 $6, $f2 # <MCInst #{{.*}} MTHC1_D32_MM
104; MM32R3:       andi16 $2, $4, 1 # <MCInst #{{.*}} ANDI16_MM
105; MM32R3:       ldc1 $f0, 16($sp) # <MCInst #{{.*}} LDC1_MM
106; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
107; MM32R3:       movn.d $f0, $f2, $2 # <MCInst #{{.*}} MOVN_I_D32_MM
108;
109; MM32R6-LABEL: tst_select_i1_double:
110; MM32R6:       # %bb.0: # %entry
111; MM32R6-NEXT:    mtc1 $7, $f1
112; MM32R6-NEXT:    mthc1 $6, $f1
113; MM32R6-NEXT:    mtc1 $4, $f0
114; MM32R6-NEXT:    ldc1 $f2, 16($sp)
115; MM32R6-NEXT:    sel.d $f0, $f2, $f1
116; MM32R6-NEXT:    jrc $ra
117entry:
118  %r = select i1 %s, double %x, double %y
119  ret double %r
120}
121
122define double @tst_select_i1_double_reordered(double %x, double %y,
123; M2-LABEL: tst_select_i1_double_reordered:
124; M2:       # %bb.0: # %entry
125; M2-NEXT:    lw $1, 16($sp)
126; M2-NEXT:    andi $1, $1, 1
127; M2-NEXT:    bnez $1, $BB1_2
128; M2-NEXT:    mov.d $f0, $f12
129; M2-NEXT:  # %bb.1: # %entry
130; M2-NEXT:    mov.d $f0, $f14
131; M2-NEXT:  $BB1_2: # %entry
132; M2-NEXT:    jr $ra
133; M2-NEXT:    nop
134;
135; CMOV32R1-LABEL: tst_select_i1_double_reordered:
136; CMOV32R1:       # %bb.0: # %entry
137; CMOV32R1-NEXT:    mov.d $f0, $f14
138; CMOV32R1-NEXT:    lw $1, 16($sp)
139; CMOV32R1-NEXT:    andi $1, $1, 1
140; CMOV32R1-NEXT:    jr $ra
141; CMOV32R1-NEXT:    movn.d $f0, $f12, $1
142;
143; CMOV32R2-LABEL: tst_select_i1_double_reordered:
144; CMOV32R2:       # %bb.0: # %entry
145; CMOV32R2-NEXT:    mov.d $f0, $f14
146; CMOV32R2-NEXT:    lw $1, 16($sp)
147; CMOV32R2-NEXT:    andi $1, $1, 1
148; CMOV32R2-NEXT:    jr $ra
149; CMOV32R2-NEXT:    movn.d $f0, $f12, $1
150;
151; 32R6-LABEL: tst_select_i1_double_reordered:
152; 32R6:       # %bb.0: # %entry
153; 32R6-NEXT:    lw $1, 16($sp)
154; 32R6-NEXT:    mtc1 $1, $f0
155; 32R6-NEXT:    jr $ra
156; 32R6-NEXT:    sel.d $f0, $f14, $f12
157;
158; M3-LABEL: tst_select_i1_double_reordered:
159; M3:       # %bb.0: # %entry
160; M3-NEXT:    andi $1, $6, 1
161; M3-NEXT:    bnez $1, .LBB1_2
162; M3-NEXT:    mov.d $f0, $f12
163; M3-NEXT:  # %bb.1: # %entry
164; M3-NEXT:    mov.d $f0, $f13
165; M3-NEXT:  .LBB1_2: # %entry
166; M3-NEXT:    jr $ra
167; M3-NEXT:    nop
168;
169; CMOV64-LABEL: tst_select_i1_double_reordered:
170; CMOV64:       # %bb.0: # %entry
171; CMOV64-NEXT:    mov.d $f0, $f13
172; CMOV64-NEXT:    andi $1, $6, 1
173; CMOV64-NEXT:    jr $ra
174; CMOV64-NEXT:    movn.d $f0, $f12, $1
175;
176; 64R6-LABEL: tst_select_i1_double_reordered:
177; 64R6:       # %bb.0: # %entry
178; 64R6-NEXT:    mtc1 $6, $f0
179; 64R6-NEXT:    jr $ra
180; 64R6-NEXT:    sel.d $f0, $f13, $f12
181;
182; MM32R3-LABEL: tst_select_i1_double_reordered:
183; MM32R3:       # %bb.0: # %entry
184; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
185; MM32R3:       lw $2, 16($sp) # <MCInst #{{.*}} LWSP_MM
186; MM32R3:       andi16 $2, $2, 1 # <MCInst #{{.*}} ANDI16_MM
187; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
188; MM32R3:       movn.d $f0, $f12, $2 # <MCInst #{{.*}} MOVN_I_D32_MM
189;
190; MM32R6-LABEL: tst_select_i1_double_reordered:
191; MM32R6:       # %bb.0: # %entry
192; MM32R6-NEXT:    lw $1, 16($sp)
193; MM32R6-NEXT:    mtc1 $1, $f0
194; MM32R6-NEXT:    sel.d $f0, $f14, $f12
195; MM32R6-NEXT:    jrc $ra
196                                              i1 signext %s) {
197entry:
198  %r = select i1 %s, double %x, double %y
199  ret double %r
200}
201
202define double @tst_select_fcmp_olt_double(double %x, double %y) {
203; M2-LABEL: tst_select_fcmp_olt_double:
204; M2:       # %bb.0: # %entry
205; M2-NEXT:    c.olt.d $f12, $f14
206; M2-NEXT:    nop
207; M2-NEXT:    bc1t $BB2_2
208; M2-NEXT:    mov.d $f0, $f12
209; M2-NEXT:  # %bb.1: # %entry
210; M2-NEXT:    mov.d $f0, $f14
211; M2-NEXT:  $BB2_2: # %entry
212; M2-NEXT:    jr $ra
213; M2-NEXT:    nop
214;
215; CMOV32R1-LABEL: tst_select_fcmp_olt_double:
216; CMOV32R1:       # %bb.0: # %entry
217; CMOV32R1-NEXT:    mov.d $f0, $f14
218; CMOV32R1-NEXT:    c.olt.d $f12, $f14
219; CMOV32R1-NEXT:    jr $ra
220; CMOV32R1-NEXT:    movt.d $f0, $f12, $fcc0
221;
222; CMOV32R2-LABEL: tst_select_fcmp_olt_double:
223; CMOV32R2:       # %bb.0: # %entry
224; CMOV32R2-NEXT:    mov.d $f0, $f14
225; CMOV32R2-NEXT:    c.olt.d $f12, $f14
226; CMOV32R2-NEXT:    jr $ra
227; CMOV32R2-NEXT:    movt.d $f0, $f12, $fcc0
228;
229; 32R6-LABEL: tst_select_fcmp_olt_double:
230; 32R6:       # %bb.0: # %entry
231; 32R6-NEXT:    cmp.lt.d $f0, $f12, $f14
232; 32R6-NEXT:    mfc1 $1, $f0
233; 32R6-NEXT:    mtc1 $1, $f0
234; 32R6-NEXT:    jr $ra
235; 32R6-NEXT:    sel.d $f0, $f14, $f12
236;
237; M3-LABEL: tst_select_fcmp_olt_double:
238; M3:       # %bb.0: # %entry
239; M3-NEXT:    c.olt.d $f12, $f13
240; M3-NEXT:    nop
241; M3-NEXT:    bc1t .LBB2_2
242; M3-NEXT:    mov.d $f0, $f12
243; M3-NEXT:  # %bb.1: # %entry
244; M3-NEXT:    mov.d $f0, $f13
245; M3-NEXT:  .LBB2_2: # %entry
246; M3-NEXT:    jr $ra
247; M3-NEXT:    nop
248;
249; CMOV64-LABEL: tst_select_fcmp_olt_double:
250; CMOV64:       # %bb.0: # %entry
251; CMOV64-NEXT:    mov.d $f0, $f13
252; CMOV64-NEXT:    c.olt.d $f12, $f13
253; CMOV64-NEXT:    jr $ra
254; CMOV64-NEXT:    movt.d $f0, $f12, $fcc0
255;
256; 64R6-LABEL: tst_select_fcmp_olt_double:
257; 64R6:       # %bb.0: # %entry
258; 64R6-NEXT:    cmp.lt.d $f0, $f12, $f13
259; 64R6-NEXT:    mfc1 $1, $f0
260; 64R6-NEXT:    mtc1 $1, $f0
261; 64R6-NEXT:    jr $ra
262; 64R6-NEXT:    sel.d $f0, $f13, $f12
263;
264; MM32R3-LABEL: tst_select_fcmp_olt_double:
265; MM32R3:       # %bb.0: # %entry
266; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
267; MM32R3:       c.olt.d $f12, $f14 # <MCInst #{{.*}} FCMP_D32_MM
268; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
269; MM32R3:       movt.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVT_D32_MM
270;
271; MM32R6-LABEL: tst_select_fcmp_olt_double:
272; MM32R6:       # %bb.0: # %entry
273; MM32R6-NEXT:    cmp.lt.d $f0, $f12, $f14
274; MM32R6-NEXT:    mfc1 $1, $f0
275; MM32R6-NEXT:    mtc1 $1, $f0
276; MM32R6-NEXT:    sel.d $f0, $f14, $f12
277; MM32R6-NEXT:    jrc $ra
278entry:
279  %s = fcmp olt double %x, %y
280  %r = select i1 %s, double %x, double %y
281  ret double %r
282}
283
284define double @tst_select_fcmp_ole_double(double %x, double %y) {
285; M2-LABEL: tst_select_fcmp_ole_double:
286; M2:       # %bb.0: # %entry
287; M2-NEXT:    c.ole.d $f12, $f14
288; M2-NEXT:    nop
289; M2-NEXT:    bc1t $BB3_2
290; M2-NEXT:    mov.d $f0, $f12
291; M2-NEXT:  # %bb.1: # %entry
292; M2-NEXT:    mov.d $f0, $f14
293; M2-NEXT:  $BB3_2: # %entry
294; M2-NEXT:    jr $ra
295; M2-NEXT:    nop
296;
297; CMOV32R1-LABEL: tst_select_fcmp_ole_double:
298; CMOV32R1:       # %bb.0: # %entry
299; CMOV32R1-NEXT:    mov.d $f0, $f14
300; CMOV32R1-NEXT:    c.ole.d $f12, $f14
301; CMOV32R1-NEXT:    jr $ra
302; CMOV32R1-NEXT:    movt.d $f0, $f12, $fcc0
303;
304; CMOV32R2-LABEL: tst_select_fcmp_ole_double:
305; CMOV32R2:       # %bb.0: # %entry
306; CMOV32R2-NEXT:    mov.d $f0, $f14
307; CMOV32R2-NEXT:    c.ole.d $f12, $f14
308; CMOV32R2-NEXT:    jr $ra
309; CMOV32R2-NEXT:    movt.d $f0, $f12, $fcc0
310;
311; 32R6-LABEL: tst_select_fcmp_ole_double:
312; 32R6:       # %bb.0: # %entry
313; 32R6-NEXT:    cmp.le.d $f0, $f12, $f14
314; 32R6-NEXT:    mfc1 $1, $f0
315; 32R6-NEXT:    mtc1 $1, $f0
316; 32R6-NEXT:    jr $ra
317; 32R6-NEXT:    sel.d $f0, $f14, $f12
318;
319; M3-LABEL: tst_select_fcmp_ole_double:
320; M3:       # %bb.0: # %entry
321; M3-NEXT:    c.ole.d $f12, $f13
322; M3-NEXT:    nop
323; M3-NEXT:    bc1t .LBB3_2
324; M3-NEXT:    mov.d $f0, $f12
325; M3-NEXT:  # %bb.1: # %entry
326; M3-NEXT:    mov.d $f0, $f13
327; M3-NEXT:  .LBB3_2: # %entry
328; M3-NEXT:    jr $ra
329; M3-NEXT:    nop
330;
331; CMOV64-LABEL: tst_select_fcmp_ole_double:
332; CMOV64:       # %bb.0: # %entry
333; CMOV64-NEXT:    mov.d $f0, $f13
334; CMOV64-NEXT:    c.ole.d $f12, $f13
335; CMOV64-NEXT:    jr $ra
336; CMOV64-NEXT:    movt.d $f0, $f12, $fcc0
337;
338; 64R6-LABEL: tst_select_fcmp_ole_double:
339; 64R6:       # %bb.0: # %entry
340; 64R6-NEXT:    cmp.le.d $f0, $f12, $f13
341; 64R6-NEXT:    mfc1 $1, $f0
342; 64R6-NEXT:    mtc1 $1, $f0
343; 64R6-NEXT:    jr $ra
344; 64R6-NEXT:    sel.d $f0, $f13, $f12
345;
346; MM32R3-LABEL: tst_select_fcmp_ole_double:
347; MM32R3:       # %bb.0: # %entry
348; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
349; MM32R3:       c.ole.d $f12, $f14 # <MCInst #{{.*}} FCMP_D32_MM
350; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
351; MM32R3:       movt.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVT_D32_MM
352;
353; MM32R6-LABEL: tst_select_fcmp_ole_double:
354; MM32R6:       # %bb.0: # %entry
355; MM32R6-NEXT:    cmp.le.d $f0, $f12, $f14
356; MM32R6-NEXT:    mfc1 $1, $f0
357; MM32R6-NEXT:    mtc1 $1, $f0
358; MM32R6-NEXT:    sel.d $f0, $f14, $f12
359; MM32R6-NEXT:    jrc $ra
360entry:
361  %s = fcmp ole double %x, %y
362  %r = select i1 %s, double %x, double %y
363  ret double %r
364}
365
366define double @tst_select_fcmp_ogt_double(double %x, double %y) {
367; M2-LABEL: tst_select_fcmp_ogt_double:
368; M2:       # %bb.0: # %entry
369; M2-NEXT:    c.ule.d $f12, $f14
370; M2-NEXT:    nop
371; M2-NEXT:    bc1f $BB4_2
372; M2-NEXT:    mov.d $f0, $f12
373; M2-NEXT:  # %bb.1: # %entry
374; M2-NEXT:    mov.d $f0, $f14
375; M2-NEXT:  $BB4_2: # %entry
376; M2-NEXT:    jr $ra
377; M2-NEXT:    nop
378;
379; CMOV32R1-LABEL: tst_select_fcmp_ogt_double:
380; CMOV32R1:       # %bb.0: # %entry
381; CMOV32R1-NEXT:    mov.d $f0, $f14
382; CMOV32R1-NEXT:    c.ule.d $f12, $f14
383; CMOV32R1-NEXT:    jr $ra
384; CMOV32R1-NEXT:    movf.d $f0, $f12, $fcc0
385;
386; CMOV32R2-LABEL: tst_select_fcmp_ogt_double:
387; CMOV32R2:       # %bb.0: # %entry
388; CMOV32R2-NEXT:    mov.d $f0, $f14
389; CMOV32R2-NEXT:    c.ule.d $f12, $f14
390; CMOV32R2-NEXT:    jr $ra
391; CMOV32R2-NEXT:    movf.d $f0, $f12, $fcc0
392;
393; 32R6-LABEL: tst_select_fcmp_ogt_double:
394; 32R6:       # %bb.0: # %entry
395; 32R6-NEXT:    cmp.lt.d $f0, $f14, $f12
396; 32R6-NEXT:    mfc1 $1, $f0
397; 32R6-NEXT:    mtc1 $1, $f0
398; 32R6-NEXT:    jr $ra
399; 32R6-NEXT:    sel.d $f0, $f14, $f12
400;
401; M3-LABEL: tst_select_fcmp_ogt_double:
402; M3:       # %bb.0: # %entry
403; M3-NEXT:    c.ule.d $f12, $f13
404; M3-NEXT:    nop
405; M3-NEXT:    bc1f .LBB4_2
406; M3-NEXT:    mov.d $f0, $f12
407; M3-NEXT:  # %bb.1: # %entry
408; M3-NEXT:    mov.d $f0, $f13
409; M3-NEXT:  .LBB4_2: # %entry
410; M3-NEXT:    jr $ra
411; M3-NEXT:    nop
412;
413; CMOV64-LABEL: tst_select_fcmp_ogt_double:
414; CMOV64:       # %bb.0: # %entry
415; CMOV64-NEXT:    mov.d $f0, $f13
416; CMOV64-NEXT:    c.ule.d $f12, $f13
417; CMOV64-NEXT:    jr $ra
418; CMOV64-NEXT:    movf.d $f0, $f12, $fcc0
419;
420; 64R6-LABEL: tst_select_fcmp_ogt_double:
421; 64R6:       # %bb.0: # %entry
422; 64R6-NEXT:    cmp.lt.d $f0, $f13, $f12
423; 64R6-NEXT:    mfc1 $1, $f0
424; 64R6-NEXT:    mtc1 $1, $f0
425; 64R6-NEXT:    jr $ra
426; 64R6-NEXT:    sel.d $f0, $f13, $f12
427;
428; MM32R3-LABEL: tst_select_fcmp_ogt_double:
429; MM32R3:       # %bb.0: # %entry
430; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
431; MM32R3:       c.ule.d $f12, $f14 # <MCInst #{{.*}} FCMP_D32_MM
432; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
433; MM32R3:       movf.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVF_D32_MM
434;
435; MM32R6-LABEL: tst_select_fcmp_ogt_double:
436; MM32R6:       # %bb.0: # %entry
437; MM32R6-NEXT:    cmp.lt.d $f0, $f14, $f12
438; MM32R6-NEXT:    mfc1 $1, $f0
439; MM32R6-NEXT:    mtc1 $1, $f0
440; MM32R6-NEXT:    sel.d $f0, $f14, $f12
441; MM32R6-NEXT:    jrc $ra
442entry:
443  %s = fcmp ogt double %x, %y
444  %r = select i1 %s, double %x, double %y
445  ret double %r
446}
447
448define double @tst_select_fcmp_oge_double(double %x, double %y) {
449; M2-LABEL: tst_select_fcmp_oge_double:
450; M2:       # %bb.0: # %entry
451; M2-NEXT:    c.ult.d $f12, $f14
452; M2-NEXT:    nop
453; M2-NEXT:    bc1f $BB5_2
454; M2-NEXT:    mov.d $f0, $f12
455; M2-NEXT:  # %bb.1: # %entry
456; M2-NEXT:    mov.d $f0, $f14
457; M2-NEXT:  $BB5_2: # %entry
458; M2-NEXT:    jr $ra
459; M2-NEXT:    nop
460;
461; CMOV32R1-LABEL: tst_select_fcmp_oge_double:
462; CMOV32R1:       # %bb.0: # %entry
463; CMOV32R1-NEXT:    mov.d $f0, $f14
464; CMOV32R1-NEXT:    c.ult.d $f12, $f14
465; CMOV32R1-NEXT:    jr $ra
466; CMOV32R1-NEXT:    movf.d $f0, $f12, $fcc0
467;
468; CMOV32R2-LABEL: tst_select_fcmp_oge_double:
469; CMOV32R2:       # %bb.0: # %entry
470; CMOV32R2-NEXT:    mov.d $f0, $f14
471; CMOV32R2-NEXT:    c.ult.d $f12, $f14
472; CMOV32R2-NEXT:    jr $ra
473; CMOV32R2-NEXT:    movf.d $f0, $f12, $fcc0
474;
475; 32R6-LABEL: tst_select_fcmp_oge_double:
476; 32R6:       # %bb.0: # %entry
477; 32R6-NEXT:    cmp.le.d $f0, $f14, $f12
478; 32R6-NEXT:    mfc1 $1, $f0
479; 32R6-NEXT:    mtc1 $1, $f0
480; 32R6-NEXT:    jr $ra
481; 32R6-NEXT:    sel.d $f0, $f14, $f12
482;
483; M3-LABEL: tst_select_fcmp_oge_double:
484; M3:       # %bb.0: # %entry
485; M3-NEXT:    c.ult.d $f12, $f13
486; M3-NEXT:    nop
487; M3-NEXT:    bc1f .LBB5_2
488; M3-NEXT:    mov.d $f0, $f12
489; M3-NEXT:  # %bb.1: # %entry
490; M3-NEXT:    mov.d $f0, $f13
491; M3-NEXT:  .LBB5_2: # %entry
492; M3-NEXT:    jr $ra
493; M3-NEXT:    nop
494;
495; CMOV64-LABEL: tst_select_fcmp_oge_double:
496; CMOV64:       # %bb.0: # %entry
497; CMOV64-NEXT:    mov.d $f0, $f13
498; CMOV64-NEXT:    c.ult.d $f12, $f13
499; CMOV64-NEXT:    jr $ra
500; CMOV64-NEXT:    movf.d $f0, $f12, $fcc0
501;
502; 64R6-LABEL: tst_select_fcmp_oge_double:
503; 64R6:       # %bb.0: # %entry
504; 64R6-NEXT:    cmp.le.d $f0, $f13, $f12
505; 64R6-NEXT:    mfc1 $1, $f0
506; 64R6-NEXT:    mtc1 $1, $f0
507; 64R6-NEXT:    jr $ra
508; 64R6-NEXT:    sel.d $f0, $f13, $f12
509;
510; MM32R3-LABEL: tst_select_fcmp_oge_double:
511; MM32R3:       # %bb.0: # %entry
512; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
513; MM32R3:       c.ult.d $f12, $f14 # <MCInst #{{.*}} FCMP_D32_MM
514; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
515; MM32R3:       movf.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVF_D32_MM
516;
517; MM32R6-LABEL: tst_select_fcmp_oge_double:
518; MM32R6:       # %bb.0: # %entry
519; MM32R6-NEXT:    cmp.le.d $f0, $f14, $f12
520; MM32R6-NEXT:    mfc1 $1, $f0
521; MM32R6-NEXT:    mtc1 $1, $f0
522; MM32R6-NEXT:    sel.d $f0, $f14, $f12
523; MM32R6-NEXT:    jrc $ra
524entry:
525  %s = fcmp oge double %x, %y
526  %r = select i1 %s, double %x, double %y
527  ret double %r
528}
529
530define double @tst_select_fcmp_oeq_double(double %x, double %y) {
531; M2-LABEL: tst_select_fcmp_oeq_double:
532; M2:       # %bb.0: # %entry
533; M2-NEXT:    c.eq.d $f12, $f14
534; M2-NEXT:    nop
535; M2-NEXT:    bc1t $BB6_2
536; M2-NEXT:    mov.d $f0, $f12
537; M2-NEXT:  # %bb.1: # %entry
538; M2-NEXT:    mov.d $f0, $f14
539; M2-NEXT:  $BB6_2: # %entry
540; M2-NEXT:    jr $ra
541; M2-NEXT:    nop
542;
543; CMOV32R1-LABEL: tst_select_fcmp_oeq_double:
544; CMOV32R1:       # %bb.0: # %entry
545; CMOV32R1-NEXT:    mov.d $f0, $f14
546; CMOV32R1-NEXT:    c.eq.d $f12, $f14
547; CMOV32R1-NEXT:    jr $ra
548; CMOV32R1-NEXT:    movt.d $f0, $f12, $fcc0
549;
550; CMOV32R2-LABEL: tst_select_fcmp_oeq_double:
551; CMOV32R2:       # %bb.0: # %entry
552; CMOV32R2-NEXT:    mov.d $f0, $f14
553; CMOV32R2-NEXT:    c.eq.d $f12, $f14
554; CMOV32R2-NEXT:    jr $ra
555; CMOV32R2-NEXT:    movt.d $f0, $f12, $fcc0
556;
557; 32R6-LABEL: tst_select_fcmp_oeq_double:
558; 32R6:       # %bb.0: # %entry
559; 32R6-NEXT:    cmp.eq.d $f0, $f12, $f14
560; 32R6-NEXT:    mfc1 $1, $f0
561; 32R6-NEXT:    mtc1 $1, $f0
562; 32R6-NEXT:    jr $ra
563; 32R6-NEXT:    sel.d $f0, $f14, $f12
564;
565; M3-LABEL: tst_select_fcmp_oeq_double:
566; M3:       # %bb.0: # %entry
567; M3-NEXT:    c.eq.d $f12, $f13
568; M3-NEXT:    nop
569; M3-NEXT:    bc1t .LBB6_2
570; M3-NEXT:    mov.d $f0, $f12
571; M3-NEXT:  # %bb.1: # %entry
572; M3-NEXT:    mov.d $f0, $f13
573; M3-NEXT:  .LBB6_2: # %entry
574; M3-NEXT:    jr $ra
575; M3-NEXT:    nop
576;
577; CMOV64-LABEL: tst_select_fcmp_oeq_double:
578; CMOV64:       # %bb.0: # %entry
579; CMOV64-NEXT:    mov.d $f0, $f13
580; CMOV64-NEXT:    c.eq.d $f12, $f13
581; CMOV64-NEXT:    jr $ra
582; CMOV64-NEXT:    movt.d $f0, $f12, $fcc0
583;
584; 64R6-LABEL: tst_select_fcmp_oeq_double:
585; 64R6:       # %bb.0: # %entry
586; 64R6-NEXT:    cmp.eq.d $f0, $f12, $f13
587; 64R6-NEXT:    mfc1 $1, $f0
588; 64R6-NEXT:    mtc1 $1, $f0
589; 64R6-NEXT:    jr $ra
590; 64R6-NEXT:    sel.d $f0, $f13, $f12
591;
592; MM32R3-LABEL: tst_select_fcmp_oeq_double:
593; MM32R3:       # %bb.0: # %entry
594; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
595; MM32R3:       c.eq.d $f12, $f14 # <MCInst #{{.*}} FCMP_D32_MM
596; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
597; MM32R3:       movt.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVT_D32_MM
598;
599; MM32R6-LABEL: tst_select_fcmp_oeq_double:
600; MM32R6:       # %bb.0: # %entry
601; MM32R6-NEXT:    cmp.eq.d $f0, $f12, $f14
602; MM32R6-NEXT:    mfc1 $1, $f0
603; MM32R6-NEXT:    mtc1 $1, $f0
604; MM32R6-NEXT:    sel.d $f0, $f14, $f12
605; MM32R6-NEXT:    jrc $ra
606entry:
607  %s = fcmp oeq double %x, %y
608  %r = select i1 %s, double %x, double %y
609  ret double %r
610}
611
612define double @tst_select_fcmp_one_double(double %x, double %y) {
613; M2-LABEL: tst_select_fcmp_one_double:
614; M2:       # %bb.0: # %entry
615; M2-NEXT:    c.ueq.d $f12, $f14
616; M2-NEXT:    nop
617; M2-NEXT:    bc1f $BB7_2
618; M2-NEXT:    mov.d $f0, $f12
619; M2-NEXT:  # %bb.1: # %entry
620; M2-NEXT:    mov.d $f0, $f14
621; M2-NEXT:  $BB7_2: # %entry
622; M2-NEXT:    jr $ra
623; M2-NEXT:    nop
624;
625; CMOV32R1-LABEL: tst_select_fcmp_one_double:
626; CMOV32R1:       # %bb.0: # %entry
627; CMOV32R1-NEXT:    mov.d $f0, $f14
628; CMOV32R1-NEXT:    c.ueq.d $f12, $f14
629; CMOV32R1-NEXT:    jr $ra
630; CMOV32R1-NEXT:    movf.d $f0, $f12, $fcc0
631;
632; CMOV32R2-LABEL: tst_select_fcmp_one_double:
633; CMOV32R2:       # %bb.0: # %entry
634; CMOV32R2-NEXT:    mov.d $f0, $f14
635; CMOV32R2-NEXT:    c.ueq.d $f12, $f14
636; CMOV32R2-NEXT:    jr $ra
637; CMOV32R2-NEXT:    movf.d $f0, $f12, $fcc0
638;
639; 32R6-LABEL: tst_select_fcmp_one_double:
640; 32R6:       # %bb.0: # %entry
641; 32R6-NEXT:    cmp.ueq.d $f0, $f12, $f14
642; 32R6-NEXT:    mfc1 $1, $f0
643; 32R6-NEXT:    not $1, $1
644; 32R6-NEXT:    mtc1 $1, $f0
645; 32R6-NEXT:    jr $ra
646; 32R6-NEXT:    sel.d $f0, $f14, $f12
647;
648; M3-LABEL: tst_select_fcmp_one_double:
649; M3:       # %bb.0: # %entry
650; M3-NEXT:    c.ueq.d $f12, $f13
651; M3-NEXT:    nop
652; M3-NEXT:    bc1f .LBB7_2
653; M3-NEXT:    mov.d $f0, $f12
654; M3-NEXT:  # %bb.1: # %entry
655; M3-NEXT:    mov.d $f0, $f13
656; M3-NEXT:  .LBB7_2: # %entry
657; M3-NEXT:    jr $ra
658; M3-NEXT:    nop
659;
660; CMOV64-LABEL: tst_select_fcmp_one_double:
661; CMOV64:       # %bb.0: # %entry
662; CMOV64-NEXT:    mov.d $f0, $f13
663; CMOV64-NEXT:    c.ueq.d $f12, $f13
664; CMOV64-NEXT:    jr $ra
665; CMOV64-NEXT:    movf.d $f0, $f12, $fcc0
666;
667; 64R6-LABEL: tst_select_fcmp_one_double:
668; 64R6:       # %bb.0: # %entry
669; 64R6-NEXT:    cmp.ueq.d $f0, $f12, $f13
670; 64R6-NEXT:    mfc1 $1, $f0
671; 64R6-NEXT:    not $1, $1
672; 64R6-NEXT:    mtc1 $1, $f0
673; 64R6-NEXT:    jr $ra
674; 64R6-NEXT:    sel.d $f0, $f13, $f12
675;
676; MM32R3-LABEL: tst_select_fcmp_one_double:
677; MM32R3:       # %bb.0: # %entry
678; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
679; MM32R3:       c.ueq.d $f12, $f14 # <MCInst #{{.*}} FCMP_D32_MM
680; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
681; MM32R3:       movf.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVF_D32_MM
682;
683; MM32R6-LABEL: tst_select_fcmp_one_double:
684; MM32R6:       # %bb.0: # %entry
685; MM32R6-NEXT:    cmp.ueq.d $f0, $f12, $f14
686; MM32R6-NEXT:    mfc1 $1, $f0
687; MM32R6-NEXT:    not $1, $1
688; MM32R6-NEXT:    mtc1 $1, $f0
689; MM32R6-NEXT:    sel.d $f0, $f14, $f12
690; MM32R6-NEXT:    jrc $ra
691entry:
692  %s = fcmp one double %x, %y
693  %r = select i1 %s, double %x, double %y
694  ret double %r
695}
696