xref: /llvm-project/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll (revision 3e0a76b1fd10d2f5f36d34a91b525c1d29685185) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -relocation-model=pic | FileCheck %s \
3; RUN:    -check-prefix=MIPS2
4; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -relocation-model=pic | FileCheck %s \
5; RUN:    -check-prefix=MIPS32
6; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \
7; RUN:    -check-prefix=MIPS32R2
8; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \
9; RUN:    -check-prefix=MIPS32R2
10; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \
11; RUN:    -check-prefix=MIPS32R2
12; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \
13; RUN:    -check-prefix=MIPS32R6
14; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -relocation-model=pic | FileCheck %s \
15; RUN:    -check-prefix=MIPS3
16; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -relocation-model=pic | FileCheck %s \
17; RUN:    -check-prefix=MIPS4
18; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -relocation-model=pic | FileCheck %s \
19; RUN:    -check-prefix=MIPS64
20; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \
21; RUN:    -check-prefix=MIPS64R2
22; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \
23; RUN:    -check-prefix=MIPS64R2
24; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \
25; RUN:    -check-prefix=MIPS64R2
26; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
27; RUN:    -check-prefix=MIPS64R6
28; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
29; RUN:    -check-prefix=MMR3
30; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
31; RUN:    -check-prefix=MMR6
32
33define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) {
34; MIPS2-LABEL: lshr_i1:
35; MIPS2:       # %bb.0: # %entry
36; MIPS2-NEXT:    jr $ra
37; MIPS2-NEXT:    move $2, $4
38;
39; MIPS32-LABEL: lshr_i1:
40; MIPS32:       # %bb.0: # %entry
41; MIPS32-NEXT:    jr $ra
42; MIPS32-NEXT:    move $2, $4
43;
44; MIPS32R2-LABEL: lshr_i1:
45; MIPS32R2:       # %bb.0: # %entry
46; MIPS32R2-NEXT:    jr $ra
47; MIPS32R2-NEXT:    move $2, $4
48;
49; MIPS32R6-LABEL: lshr_i1:
50; MIPS32R6:       # %bb.0: # %entry
51; MIPS32R6-NEXT:    jr $ra
52; MIPS32R6-NEXT:    move $2, $4
53;
54; MIPS3-LABEL: lshr_i1:
55; MIPS3:       # %bb.0: # %entry
56; MIPS3-NEXT:    jr $ra
57; MIPS3-NEXT:    move $2, $4
58;
59; MIPS4-LABEL: lshr_i1:
60; MIPS4:       # %bb.0: # %entry
61; MIPS4-NEXT:    jr $ra
62; MIPS4-NEXT:    move $2, $4
63;
64; MIPS64-LABEL: lshr_i1:
65; MIPS64:       # %bb.0: # %entry
66; MIPS64-NEXT:    jr $ra
67; MIPS64-NEXT:    move $2, $4
68;
69; MIPS64R2-LABEL: lshr_i1:
70; MIPS64R2:       # %bb.0: # %entry
71; MIPS64R2-NEXT:    jr $ra
72; MIPS64R2-NEXT:    move $2, $4
73;
74; MIPS64R6-LABEL: lshr_i1:
75; MIPS64R6:       # %bb.0: # %entry
76; MIPS64R6-NEXT:    jr $ra
77; MIPS64R6-NEXT:    move $2, $4
78;
79; MMR3-LABEL: lshr_i1:
80; MMR3:       # %bb.0: # %entry
81; MMR3-NEXT:    move $2, $4
82; MMR3-NEXT:    jrc $ra
83;
84; MMR6-LABEL: lshr_i1:
85; MMR6:       # %bb.0: # %entry
86; MMR6-NEXT:    move $2, $4
87; MMR6-NEXT:    jrc $ra
88entry:
89
90  %r = lshr i1 %a, %b
91  ret i1 %r
92}
93
94define zeroext i8 @lshr_i8(i8 zeroext %a, i8 zeroext %b) {
95; MIPS2-LABEL: lshr_i8:
96; MIPS2:       # %bb.0: # %entry
97; MIPS2-NEXT:    jr $ra
98; MIPS2-NEXT:    srlv $2, $4, $5
99;
100; MIPS32-LABEL: lshr_i8:
101; MIPS32:       # %bb.0: # %entry
102; MIPS32-NEXT:    jr $ra
103; MIPS32-NEXT:    srlv $2, $4, $5
104;
105; MIPS32R2-LABEL: lshr_i8:
106; MIPS32R2:       # %bb.0: # %entry
107; MIPS32R2-NEXT:    jr $ra
108; MIPS32R2-NEXT:    srlv $2, $4, $5
109;
110; MIPS32R6-LABEL: lshr_i8:
111; MIPS32R6:       # %bb.0: # %entry
112; MIPS32R6-NEXT:    jr $ra
113; MIPS32R6-NEXT:    srlv $2, $4, $5
114;
115; MIPS3-LABEL: lshr_i8:
116; MIPS3:       # %bb.0: # %entry
117; MIPS3-NEXT:    jr $ra
118; MIPS3-NEXT:    srlv $2, $4, $5
119;
120; MIPS4-LABEL: lshr_i8:
121; MIPS4:       # %bb.0: # %entry
122; MIPS4-NEXT:    jr $ra
123; MIPS4-NEXT:    srlv $2, $4, $5
124;
125; MIPS64-LABEL: lshr_i8:
126; MIPS64:       # %bb.0: # %entry
127; MIPS64-NEXT:    jr $ra
128; MIPS64-NEXT:    srlv $2, $4, $5
129;
130; MIPS64R2-LABEL: lshr_i8:
131; MIPS64R2:       # %bb.0: # %entry
132; MIPS64R2-NEXT:    jr $ra
133; MIPS64R2-NEXT:    srlv $2, $4, $5
134;
135; MIPS64R6-LABEL: lshr_i8:
136; MIPS64R6:       # %bb.0: # %entry
137; MIPS64R6-NEXT:    jr $ra
138; MIPS64R6-NEXT:    srlv $2, $4, $5
139;
140; MMR3-LABEL: lshr_i8:
141; MMR3:       # %bb.0: # %entry
142; MMR3-NEXT:    jr $ra
143; MMR3-NEXT:    srlv $2, $4, $5
144;
145; MMR6-LABEL: lshr_i8:
146; MMR6:       # %bb.0: # %entry
147; MMR6-NEXT:    srlv $2, $4, $5
148; MMR6-NEXT:    jrc $ra
149entry:
150
151  %r = lshr i8 %a, %b
152  ret i8 %r
153}
154
155define zeroext i16 @lshr_i16(i16 zeroext %a, i16 zeroext %b) {
156; MIPS2-LABEL: lshr_i16:
157; MIPS2:       # %bb.0: # %entry
158; MIPS2-NEXT:    jr $ra
159; MIPS2-NEXT:    srlv $2, $4, $5
160;
161; MIPS32-LABEL: lshr_i16:
162; MIPS32:       # %bb.0: # %entry
163; MIPS32-NEXT:    jr $ra
164; MIPS32-NEXT:    srlv $2, $4, $5
165;
166; MIPS32R2-LABEL: lshr_i16:
167; MIPS32R2:       # %bb.0: # %entry
168; MIPS32R2-NEXT:    jr $ra
169; MIPS32R2-NEXT:    srlv $2, $4, $5
170;
171; MIPS32R6-LABEL: lshr_i16:
172; MIPS32R6:       # %bb.0: # %entry
173; MIPS32R6-NEXT:    jr $ra
174; MIPS32R6-NEXT:    srlv $2, $4, $5
175;
176; MIPS3-LABEL: lshr_i16:
177; MIPS3:       # %bb.0: # %entry
178; MIPS3-NEXT:    jr $ra
179; MIPS3-NEXT:    srlv $2, $4, $5
180;
181; MIPS4-LABEL: lshr_i16:
182; MIPS4:       # %bb.0: # %entry
183; MIPS4-NEXT:    jr $ra
184; MIPS4-NEXT:    srlv $2, $4, $5
185;
186; MIPS64-LABEL: lshr_i16:
187; MIPS64:       # %bb.0: # %entry
188; MIPS64-NEXT:    jr $ra
189; MIPS64-NEXT:    srlv $2, $4, $5
190;
191; MIPS64R2-LABEL: lshr_i16:
192; MIPS64R2:       # %bb.0: # %entry
193; MIPS64R2-NEXT:    jr $ra
194; MIPS64R2-NEXT:    srlv $2, $4, $5
195;
196; MIPS64R6-LABEL: lshr_i16:
197; MIPS64R6:       # %bb.0: # %entry
198; MIPS64R6-NEXT:    jr $ra
199; MIPS64R6-NEXT:    srlv $2, $4, $5
200;
201; MMR3-LABEL: lshr_i16:
202; MMR3:       # %bb.0: # %entry
203; MMR3-NEXT:    jr $ra
204; MMR3-NEXT:    srlv $2, $4, $5
205;
206; MMR6-LABEL: lshr_i16:
207; MMR6:       # %bb.0: # %entry
208; MMR6-NEXT:    srlv $2, $4, $5
209; MMR6-NEXT:    jrc $ra
210entry:
211
212  %r = lshr i16 %a, %b
213  ret i16 %r
214}
215
216define signext i32 @lshr_i32(i32 signext %a, i32 signext %b) {
217; MIPS2-LABEL: lshr_i32:
218; MIPS2:       # %bb.0: # %entry
219; MIPS2-NEXT:    jr $ra
220; MIPS2-NEXT:    srlv $2, $4, $5
221;
222; MIPS32-LABEL: lshr_i32:
223; MIPS32:       # %bb.0: # %entry
224; MIPS32-NEXT:    jr $ra
225; MIPS32-NEXT:    srlv $2, $4, $5
226;
227; MIPS32R2-LABEL: lshr_i32:
228; MIPS32R2:       # %bb.0: # %entry
229; MIPS32R2-NEXT:    jr $ra
230; MIPS32R2-NEXT:    srlv $2, $4, $5
231;
232; MIPS32R6-LABEL: lshr_i32:
233; MIPS32R6:       # %bb.0: # %entry
234; MIPS32R6-NEXT:    jr $ra
235; MIPS32R6-NEXT:    srlv $2, $4, $5
236;
237; MIPS3-LABEL: lshr_i32:
238; MIPS3:       # %bb.0: # %entry
239; MIPS3-NEXT:    jr $ra
240; MIPS3-NEXT:    srlv $2, $4, $5
241;
242; MIPS4-LABEL: lshr_i32:
243; MIPS4:       # %bb.0: # %entry
244; MIPS4-NEXT:    jr $ra
245; MIPS4-NEXT:    srlv $2, $4, $5
246;
247; MIPS64-LABEL: lshr_i32:
248; MIPS64:       # %bb.0: # %entry
249; MIPS64-NEXT:    jr $ra
250; MIPS64-NEXT:    srlv $2, $4, $5
251;
252; MIPS64R2-LABEL: lshr_i32:
253; MIPS64R2:       # %bb.0: # %entry
254; MIPS64R2-NEXT:    jr $ra
255; MIPS64R2-NEXT:    srlv $2, $4, $5
256;
257; MIPS64R6-LABEL: lshr_i32:
258; MIPS64R6:       # %bb.0: # %entry
259; MIPS64R6-NEXT:    jr $ra
260; MIPS64R6-NEXT:    srlv $2, $4, $5
261;
262; MMR3-LABEL: lshr_i32:
263; MMR3:       # %bb.0: # %entry
264; MMR3-NEXT:    jr $ra
265; MMR3-NEXT:    srlv $2, $4, $5
266;
267; MMR6-LABEL: lshr_i32:
268; MMR6:       # %bb.0: # %entry
269; MMR6-NEXT:    srlv $2, $4, $5
270; MMR6-NEXT:    jrc $ra
271entry:
272
273  %r = lshr i32 %a, %b
274  ret i32 %r
275}
276
277define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) {
278; MIPS2-LABEL: lshr_i64:
279; MIPS2:       # %bb.0: # %entry
280; MIPS2-NEXT:    srlv $6, $4, $7
281; MIPS2-NEXT:    andi $1, $7, 32
282; MIPS2-NEXT:    bnez $1, $BB4_2
283; MIPS2-NEXT:    addiu $2, $zero, 0
284; MIPS2-NEXT:  # %bb.1: # %entry
285; MIPS2-NEXT:    srlv $1, $5, $7
286; MIPS2-NEXT:    xori $2, $7, 31
287; MIPS2-NEXT:    sll $3, $4, 1
288; MIPS2-NEXT:    sllv $2, $3, $2
289; MIPS2-NEXT:    or $3, $2, $1
290; MIPS2-NEXT:    jr $ra
291; MIPS2-NEXT:    move $2, $6
292; MIPS2-NEXT:  $BB4_2:
293; MIPS2-NEXT:    jr $ra
294; MIPS2-NEXT:    move $3, $6
295;
296; MIPS32-LABEL: lshr_i64:
297; MIPS32:       # %bb.0: # %entry
298; MIPS32-NEXT:    srlv $1, $5, $7
299; MIPS32-NEXT:    xori $2, $7, 31
300; MIPS32-NEXT:    sll $3, $4, 1
301; MIPS32-NEXT:    sllv $2, $3, $2
302; MIPS32-NEXT:    or $3, $2, $1
303; MIPS32-NEXT:    srlv $2, $4, $7
304; MIPS32-NEXT:    andi $1, $7, 32
305; MIPS32-NEXT:    movn $3, $2, $1
306; MIPS32-NEXT:    jr $ra
307; MIPS32-NEXT:    movn $2, $zero, $1
308;
309; MIPS32R2-LABEL: lshr_i64:
310; MIPS32R2:       # %bb.0: # %entry
311; MIPS32R2-NEXT:    srlv $1, $5, $7
312; MIPS32R2-NEXT:    xori $2, $7, 31
313; MIPS32R2-NEXT:    sll $3, $4, 1
314; MIPS32R2-NEXT:    sllv $2, $3, $2
315; MIPS32R2-NEXT:    or $3, $2, $1
316; MIPS32R2-NEXT:    srlv $2, $4, $7
317; MIPS32R2-NEXT:    andi $1, $7, 32
318; MIPS32R2-NEXT:    movn $3, $2, $1
319; MIPS32R2-NEXT:    jr $ra
320; MIPS32R2-NEXT:    movn $2, $zero, $1
321;
322; MIPS32R6-LABEL: lshr_i64:
323; MIPS32R6:       # %bb.0: # %entry
324; MIPS32R6-NEXT:    srlv $1, $5, $7
325; MIPS32R6-NEXT:    xori $2, $7, 31
326; MIPS32R6-NEXT:    sll $3, $4, 1
327; MIPS32R6-NEXT:    sllv $2, $3, $2
328; MIPS32R6-NEXT:    or $1, $2, $1
329; MIPS32R6-NEXT:    andi $2, $7, 32
330; MIPS32R6-NEXT:    seleqz $1, $1, $2
331; MIPS32R6-NEXT:    srlv $4, $4, $7
332; MIPS32R6-NEXT:    selnez $3, $4, $2
333; MIPS32R6-NEXT:    or $3, $3, $1
334; MIPS32R6-NEXT:    jr $ra
335; MIPS32R6-NEXT:    seleqz $2, $4, $2
336;
337; MIPS3-LABEL: lshr_i64:
338; MIPS3:       # %bb.0: # %entry
339; MIPS3-NEXT:    jr $ra
340; MIPS3-NEXT:    dsrlv $2, $4, $5
341;
342; MIPS4-LABEL: lshr_i64:
343; MIPS4:       # %bb.0: # %entry
344; MIPS4-NEXT:    jr $ra
345; MIPS4-NEXT:    dsrlv $2, $4, $5
346;
347; MIPS64-LABEL: lshr_i64:
348; MIPS64:       # %bb.0: # %entry
349; MIPS64-NEXT:    jr $ra
350; MIPS64-NEXT:    dsrlv $2, $4, $5
351;
352; MIPS64R2-LABEL: lshr_i64:
353; MIPS64R2:       # %bb.0: # %entry
354; MIPS64R2-NEXT:    jr $ra
355; MIPS64R2-NEXT:    dsrlv $2, $4, $5
356;
357; MIPS64R6-LABEL: lshr_i64:
358; MIPS64R6:       # %bb.0: # %entry
359; MIPS64R6-NEXT:    jr $ra
360; MIPS64R6-NEXT:    dsrlv $2, $4, $5
361;
362; MMR3-LABEL: lshr_i64:
363; MMR3:       # %bb.0: # %entry
364; MMR3-NEXT:    srlv $2, $5, $7
365; MMR3-NEXT:    xori $1, $7, 31
366; MMR3-NEXT:    sll16 $3, $4, 1
367; MMR3-NEXT:    sllv $3, $3, $1
368; MMR3-NEXT:    or16 $3, $2
369; MMR3-NEXT:    srlv $2, $4, $7
370; MMR3-NEXT:    andi16 $4, $7, 32
371; MMR3-NEXT:    movn $3, $2, $4
372; MMR3-NEXT:    li16 $5, 0
373; MMR3-NEXT:    jr $ra
374; MMR3-NEXT:    movn $2, $5, $4
375;
376; MMR6-LABEL: lshr_i64:
377; MMR6:       # %bb.0: # %entry
378; MMR6-NEXT:    srlv $1, $5, $7
379; MMR6-NEXT:    xori $2, $7, 31
380; MMR6-NEXT:    sll16 $3, $4, 1
381; MMR6-NEXT:    sllv $2, $3, $2
382; MMR6-NEXT:    or $1, $2, $1
383; MMR6-NEXT:    andi16 $2, $7, 32
384; MMR6-NEXT:    seleqz $1, $1, $2
385; MMR6-NEXT:    srlv $4, $4, $7
386; MMR6-NEXT:    selnez $3, $4, $2
387; MMR6-NEXT:    or $3, $3, $1
388; MMR6-NEXT:    seleqz $2, $4, $2
389; MMR6-NEXT:    jrc $ra
390entry:
391
392  %r = lshr i64 %a, %b
393  ret i64 %r
394}
395
396define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
397; MIPS2-LABEL: lshr_i128:
398; MIPS2:       # %bb.0: # %entry
399; MIPS2-NEXT:    addiu $sp, $sp, -32
400; MIPS2-NEXT:    .cfi_def_cfa_offset 32
401; MIPS2-NEXT:    addiu $1, $sp, 0
402; MIPS2-NEXT:    sw $7, 28($sp)
403; MIPS2-NEXT:    sw $6, 24($sp)
404; MIPS2-NEXT:    sw $5, 20($sp)
405; MIPS2-NEXT:    sw $4, 16($sp)
406; MIPS2-NEXT:    addiu $1, $1, 16
407; MIPS2-NEXT:    lw $2, 60($sp)
408; MIPS2-NEXT:    srl $3, $2, 3
409; MIPS2-NEXT:    andi $3, $3, 12
410; MIPS2-NEXT:    subu $1, $1, $3
411; MIPS2-NEXT:    sw $zero, 12($sp)
412; MIPS2-NEXT:    sw $zero, 8($sp)
413; MIPS2-NEXT:    sw $zero, 4($sp)
414; MIPS2-NEXT:    sw $zero, 0($sp)
415; MIPS2-NEXT:    lw $3, 4($1)
416; MIPS2-NEXT:    lw $5, 8($1)
417; MIPS2-NEXT:    srlv $4, $5, $2
418; MIPS2-NEXT:    sll $6, $3, 1
419; MIPS2-NEXT:    andi $7, $2, 31
420; MIPS2-NEXT:    xori $7, $7, 31
421; MIPS2-NEXT:    sllv $6, $6, $7
422; MIPS2-NEXT:    srlv $3, $3, $2
423; MIPS2-NEXT:    lw $8, 0($1)
424; MIPS2-NEXT:    sll $9, $8, 1
425; MIPS2-NEXT:    sllv $9, $9, $7
426; MIPS2-NEXT:    or $3, $3, $9
427; MIPS2-NEXT:    or $4, $4, $6
428; MIPS2-NEXT:    lw $1, 12($1)
429; MIPS2-NEXT:    srlv $1, $1, $2
430; MIPS2-NEXT:    sll $5, $5, 1
431; MIPS2-NEXT:    sllv $5, $5, $7
432; MIPS2-NEXT:    or $5, $1, $5
433; MIPS2-NEXT:    srlv $2, $8, $2
434; MIPS2-NEXT:    jr $ra
435; MIPS2-NEXT:    addiu $sp, $sp, 32
436;
437; MIPS32-LABEL: lshr_i128:
438; MIPS32:       # %bb.0: # %entry
439; MIPS32-NEXT:    addiu $sp, $sp, -32
440; MIPS32-NEXT:    .cfi_def_cfa_offset 32
441; MIPS32-NEXT:    addiu $1, $sp, 0
442; MIPS32-NEXT:    sw $7, 28($sp)
443; MIPS32-NEXT:    sw $6, 24($sp)
444; MIPS32-NEXT:    sw $5, 20($sp)
445; MIPS32-NEXT:    sw $4, 16($sp)
446; MIPS32-NEXT:    addiu $1, $1, 16
447; MIPS32-NEXT:    lw $2, 60($sp)
448; MIPS32-NEXT:    srl $3, $2, 3
449; MIPS32-NEXT:    andi $3, $3, 12
450; MIPS32-NEXT:    subu $1, $1, $3
451; MIPS32-NEXT:    sw $zero, 12($sp)
452; MIPS32-NEXT:    sw $zero, 8($sp)
453; MIPS32-NEXT:    sw $zero, 4($sp)
454; MIPS32-NEXT:    sw $zero, 0($sp)
455; MIPS32-NEXT:    lw $3, 4($1)
456; MIPS32-NEXT:    lw $5, 8($1)
457; MIPS32-NEXT:    srlv $4, $5, $2
458; MIPS32-NEXT:    sll $6, $3, 1
459; MIPS32-NEXT:    andi $7, $2, 31
460; MIPS32-NEXT:    xori $7, $7, 31
461; MIPS32-NEXT:    sllv $6, $6, $7
462; MIPS32-NEXT:    srlv $3, $3, $2
463; MIPS32-NEXT:    lw $8, 0($1)
464; MIPS32-NEXT:    sll $9, $8, 1
465; MIPS32-NEXT:    sllv $9, $9, $7
466; MIPS32-NEXT:    or $3, $3, $9
467; MIPS32-NEXT:    or $4, $4, $6
468; MIPS32-NEXT:    lw $1, 12($1)
469; MIPS32-NEXT:    srlv $1, $1, $2
470; MIPS32-NEXT:    sll $5, $5, 1
471; MIPS32-NEXT:    sllv $5, $5, $7
472; MIPS32-NEXT:    or $5, $1, $5
473; MIPS32-NEXT:    srlv $2, $8, $2
474; MIPS32-NEXT:    jr $ra
475; MIPS32-NEXT:    addiu $sp, $sp, 32
476;
477; MIPS32R2-LABEL: lshr_i128:
478; MIPS32R2:       # %bb.0: # %entry
479; MIPS32R2-NEXT:    addiu $sp, $sp, -32
480; MIPS32R2-NEXT:    .cfi_def_cfa_offset 32
481; MIPS32R2-NEXT:    addiu $1, $sp, 0
482; MIPS32R2-NEXT:    sw $7, 28($sp)
483; MIPS32R2-NEXT:    sw $6, 24($sp)
484; MIPS32R2-NEXT:    sw $5, 20($sp)
485; MIPS32R2-NEXT:    sw $4, 16($sp)
486; MIPS32R2-NEXT:    addiu $1, $1, 16
487; MIPS32R2-NEXT:    lw $2, 60($sp)
488; MIPS32R2-NEXT:    srl $3, $2, 3
489; MIPS32R2-NEXT:    andi $3, $3, 12
490; MIPS32R2-NEXT:    subu $1, $1, $3
491; MIPS32R2-NEXT:    sw $zero, 12($sp)
492; MIPS32R2-NEXT:    sw $zero, 8($sp)
493; MIPS32R2-NEXT:    sw $zero, 4($sp)
494; MIPS32R2-NEXT:    sw $zero, 0($sp)
495; MIPS32R2-NEXT:    lw $3, 4($1)
496; MIPS32R2-NEXT:    lw $5, 8($1)
497; MIPS32R2-NEXT:    srlv $4, $5, $2
498; MIPS32R2-NEXT:    sll $6, $3, 1
499; MIPS32R2-NEXT:    andi $7, $2, 31
500; MIPS32R2-NEXT:    xori $7, $7, 31
501; MIPS32R2-NEXT:    sllv $6, $6, $7
502; MIPS32R2-NEXT:    srlv $3, $3, $2
503; MIPS32R2-NEXT:    lw $8, 0($1)
504; MIPS32R2-NEXT:    sll $9, $8, 1
505; MIPS32R2-NEXT:    sllv $9, $9, $7
506; MIPS32R2-NEXT:    or $3, $3, $9
507; MIPS32R2-NEXT:    or $4, $4, $6
508; MIPS32R2-NEXT:    lw $1, 12($1)
509; MIPS32R2-NEXT:    srlv $1, $1, $2
510; MIPS32R2-NEXT:    sll $5, $5, 1
511; MIPS32R2-NEXT:    sllv $5, $5, $7
512; MIPS32R2-NEXT:    or $5, $1, $5
513; MIPS32R2-NEXT:    srlv $2, $8, $2
514; MIPS32R2-NEXT:    jr $ra
515; MIPS32R2-NEXT:    addiu $sp, $sp, 32
516;
517; MIPS32R6-LABEL: lshr_i128:
518; MIPS32R6:       # %bb.0: # %entry
519; MIPS32R6-NEXT:    addiu $sp, $sp, -32
520; MIPS32R6-NEXT:    .cfi_def_cfa_offset 32
521; MIPS32R6-NEXT:    addiu $1, $sp, 0
522; MIPS32R6-NEXT:    sw $7, 28($sp)
523; MIPS32R6-NEXT:    sw $6, 24($sp)
524; MIPS32R6-NEXT:    sw $5, 20($sp)
525; MIPS32R6-NEXT:    sw $4, 16($sp)
526; MIPS32R6-NEXT:    addiu $1, $1, 16
527; MIPS32R6-NEXT:    lw $2, 60($sp)
528; MIPS32R6-NEXT:    srl $3, $2, 3
529; MIPS32R6-NEXT:    andi $3, $3, 12
530; MIPS32R6-NEXT:    subu $1, $1, $3
531; MIPS32R6-NEXT:    sw $zero, 12($sp)
532; MIPS32R6-NEXT:    sw $zero, 8($sp)
533; MIPS32R6-NEXT:    sw $zero, 4($sp)
534; MIPS32R6-NEXT:    sw $zero, 0($sp)
535; MIPS32R6-NEXT:    lw $3, 4($1)
536; MIPS32R6-NEXT:    lw $5, 8($1)
537; MIPS32R6-NEXT:    srlv $4, $5, $2
538; MIPS32R6-NEXT:    sll $6, $3, 1
539; MIPS32R6-NEXT:    andi $7, $2, 31
540; MIPS32R6-NEXT:    xori $7, $7, 31
541; MIPS32R6-NEXT:    sllv $6, $6, $7
542; MIPS32R6-NEXT:    srlv $3, $3, $2
543; MIPS32R6-NEXT:    lw $8, 0($1)
544; MIPS32R6-NEXT:    sll $9, $8, 1
545; MIPS32R6-NEXT:    sllv $9, $9, $7
546; MIPS32R6-NEXT:    or $3, $3, $9
547; MIPS32R6-NEXT:    or $4, $4, $6
548; MIPS32R6-NEXT:    lw $1, 12($1)
549; MIPS32R6-NEXT:    srlv $1, $1, $2
550; MIPS32R6-NEXT:    sll $5, $5, 1
551; MIPS32R6-NEXT:    sllv $5, $5, $7
552; MIPS32R6-NEXT:    or $5, $1, $5
553; MIPS32R6-NEXT:    srlv $2, $8, $2
554; MIPS32R6-NEXT:    jr $ra
555; MIPS32R6-NEXT:    addiu $sp, $sp, 32
556;
557; MIPS3-LABEL: lshr_i128:
558; MIPS3:       # %bb.0: # %entry
559; MIPS3-NEXT:    sll $3, $7, 0
560; MIPS3-NEXT:    dsrlv $6, $4, $7
561; MIPS3-NEXT:    andi $1, $3, 64
562; MIPS3-NEXT:    bnez $1, .LBB5_2
563; MIPS3-NEXT:    daddiu $2, $zero, 0
564; MIPS3-NEXT:  # %bb.1: # %entry
565; MIPS3-NEXT:    dsrlv $1, $5, $7
566; MIPS3-NEXT:    dsll $2, $4, 1
567; MIPS3-NEXT:    xori $3, $3, 63
568; MIPS3-NEXT:    dsllv $2, $2, $3
569; MIPS3-NEXT:    or $3, $2, $1
570; MIPS3-NEXT:    jr $ra
571; MIPS3-NEXT:    move $2, $6
572; MIPS3-NEXT:  .LBB5_2:
573; MIPS3-NEXT:    jr $ra
574; MIPS3-NEXT:    move $3, $6
575;
576; MIPS4-LABEL: lshr_i128:
577; MIPS4:       # %bb.0: # %entry
578; MIPS4-NEXT:    dsrlv $1, $5, $7
579; MIPS4-NEXT:    dsll $2, $4, 1
580; MIPS4-NEXT:    sll $5, $7, 0
581; MIPS4-NEXT:    xori $3, $5, 63
582; MIPS4-NEXT:    dsllv $2, $2, $3
583; MIPS4-NEXT:    or $3, $2, $1
584; MIPS4-NEXT:    dsrlv $2, $4, $7
585; MIPS4-NEXT:    andi $1, $5, 64
586; MIPS4-NEXT:    movn $3, $2, $1
587; MIPS4-NEXT:    jr $ra
588; MIPS4-NEXT:    movn $2, $zero, $1
589;
590; MIPS64-LABEL: lshr_i128:
591; MIPS64:       # %bb.0: # %entry
592; MIPS64-NEXT:    dsrlv $1, $5, $7
593; MIPS64-NEXT:    dsll $2, $4, 1
594; MIPS64-NEXT:    sll $5, $7, 0
595; MIPS64-NEXT:    xori $3, $5, 63
596; MIPS64-NEXT:    dsllv $2, $2, $3
597; MIPS64-NEXT:    or $3, $2, $1
598; MIPS64-NEXT:    dsrlv $2, $4, $7
599; MIPS64-NEXT:    andi $1, $5, 64
600; MIPS64-NEXT:    movn $3, $2, $1
601; MIPS64-NEXT:    jr $ra
602; MIPS64-NEXT:    movn $2, $zero, $1
603;
604; MIPS64R2-LABEL: lshr_i128:
605; MIPS64R2:       # %bb.0: # %entry
606; MIPS64R2-NEXT:    dsrlv $1, $5, $7
607; MIPS64R2-NEXT:    dsll $2, $4, 1
608; MIPS64R2-NEXT:    sll $5, $7, 0
609; MIPS64R2-NEXT:    xori $3, $5, 63
610; MIPS64R2-NEXT:    dsllv $2, $2, $3
611; MIPS64R2-NEXT:    or $3, $2, $1
612; MIPS64R2-NEXT:    dsrlv $2, $4, $7
613; MIPS64R2-NEXT:    andi $1, $5, 64
614; MIPS64R2-NEXT:    movn $3, $2, $1
615; MIPS64R2-NEXT:    jr $ra
616; MIPS64R2-NEXT:    movn $2, $zero, $1
617;
618; MIPS64R6-LABEL: lshr_i128:
619; MIPS64R6:       # %bb.0: # %entry
620; MIPS64R6-NEXT:    dsrlv $1, $5, $7
621; MIPS64R6-NEXT:    dsll $2, $4, 1
622; MIPS64R6-NEXT:    sll $3, $7, 0
623; MIPS64R6-NEXT:    xori $5, $3, 63
624; MIPS64R6-NEXT:    dsllv $2, $2, $5
625; MIPS64R6-NEXT:    or $1, $2, $1
626; MIPS64R6-NEXT:    andi $2, $3, 64
627; MIPS64R6-NEXT:    sll $2, $2, 0
628; MIPS64R6-NEXT:    seleqz $1, $1, $2
629; MIPS64R6-NEXT:    dsrlv $4, $4, $7
630; MIPS64R6-NEXT:    selnez $3, $4, $2
631; MIPS64R6-NEXT:    or $3, $3, $1
632; MIPS64R6-NEXT:    jr $ra
633; MIPS64R6-NEXT:    seleqz $2, $4, $2
634;
635; MMR3-LABEL: lshr_i128:
636; MMR3:       # %bb.0: # %entry
637; MMR3-NEXT:    addiusp -40
638; MMR3-NEXT:    .cfi_def_cfa_offset 40
639; MMR3-NEXT:    swp $16, 32($sp)
640; MMR3-NEXT:    .cfi_offset 17, -4
641; MMR3-NEXT:    .cfi_offset 16, -8
642; MMR3-NEXT:    li16 $2, 0
643; MMR3-NEXT:    swp $6, 24($sp)
644; MMR3-NEXT:    swp $4, 16($sp)
645; MMR3-NEXT:    sw $2, 12($sp)
646; MMR3-NEXT:    sw $2, 8($sp)
647; MMR3-NEXT:    sw $2, 4($sp)
648; MMR3-NEXT:    sw $2, 0($sp)
649; MMR3-NEXT:    addiur1sp $2, 0
650; MMR3-NEXT:    addiur2 $2, $2, 16
651; MMR3-NEXT:    lw $3, 68($sp)
652; MMR3-NEXT:    srl16 $4, $3, 3
653; MMR3-NEXT:    andi $4, $4, 12
654; MMR3-NEXT:    subu16 $5, $2, $4
655; MMR3-NEXT:    lwp $6, 4($5)
656; MMR3-NEXT:    andi16 $2, $3, 31
657; MMR3-NEXT:    srlv $16, $7, $2
658; MMR3-NEXT:    sll16 $3, $6, 1
659; MMR3-NEXT:    xori $1, $2, 31
660; MMR3-NEXT:    sllv $4, $3, $1
661; MMR3-NEXT:    srlv $6, $6, $2
662; MMR3-NEXT:    lw16 $17, 0($5)
663; MMR3-NEXT:    sll16 $3, $17, 1
664; MMR3-NEXT:    sllv $3, $3, $1
665; MMR3-NEXT:    or16 $3, $6
666; MMR3-NEXT:    or16 $4, $16
667; MMR3-NEXT:    lw16 $5, 12($5)
668; MMR3-NEXT:    srlv $6, $5, $2
669; MMR3-NEXT:    sll16 $5, $7, 1
670; MMR3-NEXT:    sllv $5, $5, $1
671; MMR3-NEXT:    or16 $5, $6
672; MMR3-NEXT:    srlv $2, $17, $2
673; MMR3-NEXT:    lwp $16, 32($sp)
674; MMR3-NEXT:    addiusp 40
675; MMR3-NEXT:    jrc $ra
676;
677; MMR6-LABEL: lshr_i128:
678; MMR6:       # %bb.0: # %entry
679; MMR6-NEXT:    addiu $sp, $sp, -40
680; MMR6-NEXT:    .cfi_def_cfa_offset 40
681; MMR6-NEXT:    sw $16, 36($sp) # 4-byte Folded Spill
682; MMR6-NEXT:    .cfi_offset 16, -4
683; MMR6-NEXT:    li16 $2, 0
684; MMR6-NEXT:    sw $7, 28($sp)
685; MMR6-NEXT:    sw $6, 24($sp)
686; MMR6-NEXT:    sw $5, 20($sp)
687; MMR6-NEXT:    sw $4, 16($sp)
688; MMR6-NEXT:    sw $2, 12($sp)
689; MMR6-NEXT:    sw $2, 8($sp)
690; MMR6-NEXT:    sw $2, 4($sp)
691; MMR6-NEXT:    sw $2, 0($sp)
692; MMR6-NEXT:    addiu $2, $sp, 0
693; MMR6-NEXT:    addiur2 $2, $2, 16
694; MMR6-NEXT:    lw $3, 68($sp)
695; MMR6-NEXT:    srl16 $4, $3, 3
696; MMR6-NEXT:    andi $4, $4, 12
697; MMR6-NEXT:    subu16 $2, $2, $4
698; MMR6-NEXT:    lw16 $4, 4($2)
699; MMR6-NEXT:    lw16 $5, 8($2)
700; MMR6-NEXT:    andi16 $6, $3, 31
701; MMR6-NEXT:    srlv $1, $5, $6
702; MMR6-NEXT:    sll16 $3, $4, 1
703; MMR6-NEXT:    xori $7, $6, 31
704; MMR6-NEXT:    sllv $8, $3, $7
705; MMR6-NEXT:    srlv $3, $4, $6
706; MMR6-NEXT:    lw16 $16, 0($2)
707; MMR6-NEXT:    sll16 $4, $16, 1
708; MMR6-NEXT:    sllv $4, $4, $7
709; MMR6-NEXT:    or $3, $3, $4
710; MMR6-NEXT:    or $4, $1, $8
711; MMR6-NEXT:    lw16 $2, 12($2)
712; MMR6-NEXT:    srlv $1, $2, $6
713; MMR6-NEXT:    sll16 $2, $5, 1
714; MMR6-NEXT:    sllv $2, $2, $7
715; MMR6-NEXT:    or $5, $1, $2
716; MMR6-NEXT:    srlv $2, $16, $6
717; MMR6-NEXT:    lw $16, 36($sp) # 4-byte Folded Reload
718; MMR6-NEXT:    addiu $sp, $sp, 40
719; MMR6-NEXT:    jrc $ra
720entry:
721
722; o32 shouldn't use TImode helpers.
723; GP32-NOT:       lw        $25, %call16(__lshrti3)($gp)
724; MM-NOT:         lw        $25, %call16(__lshrti3)($2)
725
726  %r = lshr i128 %a, %b
727  ret i128 %r
728}
729