xref: /llvm-project/llvm/test/CodeGen/Mips/llvm-ir/abs.ll (revision ae26f50aea4ef1a6c7058019f0db11a91bbcdade)
1; RUN: llc -mtriple=mips -mcpu=mips32                                    -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
2; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+abs2008,+fp64            -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
3; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+abs2008,+micromips       -asm-show-inst < %s | FileCheck %s --check-prefix=MM
4; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+abs2008,+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
5; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips                -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
6
7define float @abs_s(float %a) {
8; MIPS32: {{(ori|ins)}}
9; MIPS32-NOT: abs.s
10; MIPS32FP64: abs.s  {{.*}}               # <MCInst #{{[0-9]+}} FABS_S
11; MM:         abs.s  {{.*}}               # <MCInst #{{[0-9]+}} FABS_S_MM
12; MMFP64:     abs.s  {{.*}}               # <MCInst #{{[0-9]+}} FABS_S_MM
13; MMR6:       abs.s  {{.*}}               # <MCInst #{{[0-9]+}} FABS_S_MM
14    %ret = call float @llvm.fabs.f32(float %a)
15    ret float %ret
16}
17
18define double @abs_d(double %a) {
19; MIPS32: {{(ori|ins|dsll)}}
20; MIPS32-NOT: abs.d
21; MIPS32FP64: abs.d  {{.*}}               # <MCInst #{{[0-9]+}} FABS_D64
22; MM:         abs.d  {{.*}}               # <MCInst #{{[0-9]+}} FABS_D32_MM
23; MMFP64:     abs.d  {{.*}}               # <MCInst #{{[0-9]+}} FABS_D64_MM
24; MMR6:       abs.d  {{.*}}               # <MCInst #{{[0-9]+}} FABS_D64_MM
25    %ret = call double @llvm.fabs.f64(double %a)
26    ret double %ret
27}
28
29declare float @llvm.fabs.f32(float %a)
30declare double @llvm.fabs.f64(double %a)
31