xref: /llvm-project/llvm/test/CodeGen/Mips/cstmaterialization/stack.ll (revision ae26f50aea4ef1a6c7058019f0db11a91bbcdade)
1; RUN: llc -mtriple=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=CHECK-MIPS32
2; RUN: llc -mtriple=mips64el -mcpu=mips64 -relocation-model=pic < %s | \
3; RUN:      FileCheck %s -check-prefix=CHECK-MIPS64
4; RUN: llc -mtriple=mipsel -mcpu=mips64 -target-abi n32 < %s | \
5; RUN:      FileCheck %s -check-prefix=CHECK-MIPSN32
6
7; Test that the expansion of ADJCALLSTACKDOWN and ADJCALLSTACKUP generate
8; (d)subu and (d)addu rather than just (d)addu. The (d)subu sequences are
9; generally shorter as the constant that has to be materialized is smaller.
10
11define i32 @main() {
12entry:
13  %z = alloca [1048576 x i8], align 1
14  %call = call i32 @foo(ptr %z)
15  ret i32 0
16; CHECK-LABEL: main
17
18; CHECK-MIPS32: lui   $[[R0:[0-9]+]], 16
19; CHECK-MIPS32: addiu $[[R0]], $[[R0]], 24
20; CHECK-MIPS32: subu  $sp, $sp, $[[R0]]
21
22; CHECK-MIPS32: lui   $[[R1:[0-9]+]], 16
23; CHECK-MIPS32: addiu $[[R1]], $[[R1]], 24
24; CHECK-MIPS32: addu  $sp, $sp, $[[R1]]
25
26; CHECK-MIPS64: lui     $[[R0:[0-9]+]], 1
27; CHECK-MIPS64: daddiu  $[[R0]], $[[R0]], 32
28; CHECK-MIPS64: dsubu   $sp, $sp, $[[R0]]
29
30; FIXME:
31; These are here to match other lui's used in address computations. We need to
32; investigate why address computations are not CSE'd. Or implement it.
33
34; CHECK-MIPS64: lui
35; CHECK-MIPS64: lui
36; CHECK-MIPS64: lui
37; CHECK-MIPS64: lui
38
39; CHECK-MIPS64: lui     $[[R1:[0-9]+]], 16
40; CHECK-MIPS64: daddiu  $[[R1]], $[[R1]], 32
41; CHECK-MIPS64: daddu   $sp, $sp, $[[R1]]
42
43; CHECK-MIPSN32: lui   $[[R0:[0-9]+]], 16
44; CHECK-MIPSN32: addiu $[[R0]], $[[R0]], 16
45; CHECK-MIPSN32: subu  $sp, $sp, $[[R0]]
46
47; CHECK-MIPSN32: lui   $[[R1:[0-9]+]], 16
48; CHECK-MIPSN32: addiu $[[R1]], $[[R1]], 16
49; CHECK-MIPSN32: addu  $sp, $sp, $[[R1]]
50
51}
52
53declare i32 @foo(ptr)
54