xref: /llvm-project/llvm/test/CodeGen/Mips/cpus.ll (revision 80b3dcc045f8ea6e5e532d8891bbf1305bce89e8)
1; Check that the CPU names work.
2
3; RUN: llc -mtriple=mips -mcpu=generic -filetype=obj < %s \
4; RUN:   | llvm-readelf -A - | FileCheck %s --check-prefix=GENERIC
5; GENERIC: ISA: MIPS32
6
7; RUN: llc -mtriple=mips -mcpu=mips1 -filetype=obj < %s \
8; RUN:   | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS1
9; MIPS1: ISA: MIPS1
10; RUN: llc -mtriple=mips -mcpu=mips2 -filetype=obj < %s \
11; RUN:   | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS2
12; MIPS2: ISA: MIPS2
13; RUN: llc -mtriple=mips64 -mcpu=mips3 -filetype=obj < %s \
14; RUN:   | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS3
15; MIPS3: ISA: MIPS3
16; RUN: llc -mtriple=mips64 -mcpu=mips4 -filetype=obj < %s \
17; RUN:   | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS4
18; MIPS4: ISA: MIPS4
19
20; RUN: llc -mtriple=mips -mcpu=mips32 -filetype=obj < %s \
21; RUN:   | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS32
22; MIPS32: ISA: MIPS32
23; RUN: llc -mtriple=mips -mcpu=mips32r2 -filetype=obj < %s \
24; RUN:   | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS32R2
25; MIPS32R2: ISA: MIPS32r2
26; RUN: llc -mtriple=mips -mcpu=mips32r3 -filetype=obj < %s \
27; RUN:   | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS32R3
28; MIPS32R3: ISA: MIPS32r3
29; RUN: llc -mtriple=mips -mcpu=mips32r5 -filetype=obj < %s \
30; RUN:   | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS32R5
31; MIPS32R5: ISA: MIPS32r5
32; RUN: llc -mtriple=mips -mcpu=mips32r6 -filetype=obj < %s \
33; RUN:   | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS32R6
34; MIPS32R6: ISA: MIPS32r6
35
36; RUN: llc -mtriple=mips64 -mcpu=mips64 -filetype=obj < %s \
37; RUN:   | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS64
38; MIPS64: ISA: MIPS64
39; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -filetype=obj < %s \
40; RUN:   | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS64R2
41; MIPS64R2: ISA: MIPS64r2
42; RUN: llc -mtriple=mips64 -mcpu=mips64r3 -filetype=obj < %s \
43; RUN:   | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS64R3
44; MIPS64R3: ISA: MIPS64r3
45; RUN: llc -mtriple=mips64 -mcpu=mips64r5 -filetype=obj < %s \
46; RUN:   | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS64R5
47; MIPS64R5: ISA: MIPS64r5
48; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -filetype=obj < %s \
49; RUN:   | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS64R6
50; MIPS64R6: ISA: MIPS64r6
51
52; RUN: llc -mtriple=mips64 -mcpu=octeon -filetype=obj < %s \
53; RUN:   | llvm-readelf -A - | FileCheck %s --check-prefix=OCTEON
54; OCTEON: ISA: MIPS64r2
55; OCTEON: ISA Extension: Cavium Networks Octeon
56; RUN: llc -mtriple=mips64 -mcpu=octeon+ -filetype=obj < %s \
57; RUN:   | llvm-readelf -A - | FileCheck %s --check-prefix=OCTEONP
58; OCTEONP: ISA: MIPS64r2
59; OCTEONP: ISA Extension: Cavium Networks OcteonP
60
61; Check that we reject CPUs that are not implemented.
62
63; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips5 2>&1 \
64; RUN:   | FileCheck %s --check-prefix=ERROR
65
66; ERROR: LLVM ERROR: Code generation for MIPS-{{.}} is not implemented
67
68define void @foo() {
69  ret void
70}
71