xref: /llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div_vec_builtin.ll (revision 8663926a544602932d299dda435ed1ef70a05f48) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
3
4declare <16 x i8> @llvm.mips.div.s.b(<16 x i8>, <16 x i8>)
5define void @sdiv_v16i8_builtin(ptr %a, ptr %b, ptr %c) {
6; P5600-LABEL: sdiv_v16i8_builtin:
7; P5600:       # %bb.0: # %entry
8; P5600-NEXT:    ld.b $w0, 0($4)
9; P5600-NEXT:    ld.b $w1, 0($5)
10; P5600-NEXT:    div_s.b $w0, $w0, $w1
11; P5600-NEXT:    st.b $w0, 0($6)
12; P5600-NEXT:    jr $ra
13; P5600-NEXT:    nop
14entry:
15  %0 = load <16 x i8>, ptr %a, align 16
16  %1 = load <16 x i8>, ptr %b, align 16
17  %2 = tail call <16 x i8> @llvm.mips.div.s.b(<16 x i8> %0, <16 x i8> %1)
18  store <16 x i8> %2, ptr %c, align 16
19  ret void
20}
21
22declare <8 x i16> @llvm.mips.div.s.h(<8 x i16>, <8 x i16>)
23define void @sdiv_v8i16_builtin(ptr %a, ptr %b, ptr %c) {
24; P5600-LABEL: sdiv_v8i16_builtin:
25; P5600:       # %bb.0: # %entry
26; P5600-NEXT:    ld.h $w0, 0($4)
27; P5600-NEXT:    ld.h $w1, 0($5)
28; P5600-NEXT:    div_s.h $w0, $w0, $w1
29; P5600-NEXT:    st.h $w0, 0($6)
30; P5600-NEXT:    jr $ra
31; P5600-NEXT:    nop
32entry:
33  %0 = load <8 x i16>, ptr %a, align 16
34  %1 = load <8 x i16>, ptr %b, align 16
35  %2 = tail call <8 x i16> @llvm.mips.div.s.h(<8 x i16> %0, <8 x i16> %1)
36  store <8 x i16> %2, ptr %c, align 16
37  ret void
38}
39
40declare <4 x i32> @llvm.mips.div.s.w(<4 x i32>, <4 x i32>)
41define void @sdiv_v4i32_builtin(ptr %a, ptr %b, ptr %c) {
42; P5600-LABEL: sdiv_v4i32_builtin:
43; P5600:       # %bb.0: # %entry
44; P5600-NEXT:    ld.w $w0, 0($4)
45; P5600-NEXT:    ld.w $w1, 0($5)
46; P5600-NEXT:    div_s.w $w0, $w0, $w1
47; P5600-NEXT:    st.w $w0, 0($6)
48; P5600-NEXT:    jr $ra
49; P5600-NEXT:    nop
50entry:
51  %0 = load <4 x i32>, ptr %a, align 16
52  %1 = load <4 x i32>, ptr %b, align 16
53  %2 = tail call <4 x i32> @llvm.mips.div.s.w(<4 x i32> %0, <4 x i32> %1)
54  store <4 x i32> %2, ptr %c, align 16
55  ret void
56}
57
58declare <2 x i64> @llvm.mips.div.s.d(<2 x i64>, <2 x i64>)
59define void @sdiv_v2i64_builtin(ptr %a, ptr %b, ptr %c) {
60; P5600-LABEL: sdiv_v2i64_builtin:
61; P5600:       # %bb.0: # %entry
62; P5600-NEXT:    ld.d $w0, 0($4)
63; P5600-NEXT:    ld.d $w1, 0($5)
64; P5600-NEXT:    div_s.d $w0, $w0, $w1
65; P5600-NEXT:    st.d $w0, 0($6)
66; P5600-NEXT:    jr $ra
67; P5600-NEXT:    nop
68entry:
69  %0 = load <2 x i64>, ptr %a, align 16
70  %1 = load <2 x i64>, ptr %b, align 16
71  %2 = tail call <2 x i64> @llvm.mips.div.s.d(<2 x i64> %0, <2 x i64> %1)
72  store <2 x i64> %2, ptr %c, align 16
73  ret void
74}
75
76declare <16 x i8> @llvm.mips.mod.s.b(<16 x i8>, <16 x i8>)
77define void @smod_v16i8_builtin(ptr %a, ptr %b, ptr %c) {
78; P5600-LABEL: smod_v16i8_builtin:
79; P5600:       # %bb.0: # %entry
80; P5600-NEXT:    ld.b $w0, 0($4)
81; P5600-NEXT:    ld.b $w1, 0($5)
82; P5600-NEXT:    mod_s.b $w0, $w0, $w1
83; P5600-NEXT:    st.b $w0, 0($6)
84; P5600-NEXT:    jr $ra
85; P5600-NEXT:    nop
86entry:
87  %0 = load <16 x i8>, ptr %a, align 16
88  %1 = load <16 x i8>, ptr %b, align 16
89  %2 = tail call <16 x i8> @llvm.mips.mod.s.b(<16 x i8> %0, <16 x i8> %1)
90  store <16 x i8> %2, ptr %c, align 16
91  ret void
92}
93
94declare <8 x i16> @llvm.mips.mod.s.h(<8 x i16>, <8 x i16>)
95define void @smod_v8i16_builtin(ptr %a, ptr %b, ptr %c) {
96; P5600-LABEL: smod_v8i16_builtin:
97; P5600:       # %bb.0: # %entry
98; P5600-NEXT:    ld.h $w0, 0($4)
99; P5600-NEXT:    ld.h $w1, 0($5)
100; P5600-NEXT:    mod_s.h $w0, $w0, $w1
101; P5600-NEXT:    st.h $w0, 0($6)
102; P5600-NEXT:    jr $ra
103; P5600-NEXT:    nop
104entry:
105  %0 = load <8 x i16>, ptr %a, align 16
106  %1 = load <8 x i16>, ptr %b, align 16
107  %2 = tail call <8 x i16> @llvm.mips.mod.s.h(<8 x i16> %0, <8 x i16> %1)
108  store <8 x i16> %2, ptr %c, align 16
109  ret void
110}
111
112declare <4 x i32> @llvm.mips.mod.s.w(<4 x i32>, <4 x i32>)
113define void @smod_v4i32_builtin(ptr %a, ptr %b, ptr %c) {
114; P5600-LABEL: smod_v4i32_builtin:
115; P5600:       # %bb.0: # %entry
116; P5600-NEXT:    ld.w $w0, 0($4)
117; P5600-NEXT:    ld.w $w1, 0($5)
118; P5600-NEXT:    mod_s.w $w0, $w0, $w1
119; P5600-NEXT:    st.w $w0, 0($6)
120; P5600-NEXT:    jr $ra
121; P5600-NEXT:    nop
122entry:
123  %0 = load <4 x i32>, ptr %a, align 16
124  %1 = load <4 x i32>, ptr %b, align 16
125  %2 = tail call <4 x i32> @llvm.mips.mod.s.w(<4 x i32> %0, <4 x i32> %1)
126  store <4 x i32> %2, ptr %c, align 16
127  ret void
128}
129
130declare <2 x i64> @llvm.mips.mod.s.d(<2 x i64>, <2 x i64>)
131define void @smod_v2i64_builtin(ptr %a, ptr %b, ptr %c) {
132; P5600-LABEL: smod_v2i64_builtin:
133; P5600:       # %bb.0: # %entry
134; P5600-NEXT:    ld.d $w0, 0($4)
135; P5600-NEXT:    ld.d $w1, 0($5)
136; P5600-NEXT:    mod_s.d $w0, $w0, $w1
137; P5600-NEXT:    st.d $w0, 0($6)
138; P5600-NEXT:    jr $ra
139; P5600-NEXT:    nop
140entry:
141  %0 = load <2 x i64>, ptr %a, align 16
142  %1 = load <2 x i64>, ptr %b, align 16
143  %2 = tail call <2 x i64> @llvm.mips.mod.s.d(<2 x i64> %0, <2 x i64> %1)
144  store <2 x i64> %2, ptr %c, align 16
145  ret void
146}
147
148declare <16 x i8> @llvm.mips.div.u.b(<16 x i8>, <16 x i8>)
149define void @udiv_v16u8_builtin(ptr %a, ptr %b, ptr %c) {
150; P5600-LABEL: udiv_v16u8_builtin:
151; P5600:       # %bb.0: # %entry
152; P5600-NEXT:    ld.b $w0, 0($4)
153; P5600-NEXT:    ld.b $w1, 0($5)
154; P5600-NEXT:    div_u.b $w0, $w0, $w1
155; P5600-NEXT:    st.b $w0, 0($6)
156; P5600-NEXT:    jr $ra
157; P5600-NEXT:    nop
158entry:
159  %0 = load <16 x i8>, ptr %a, align 16
160  %1 = load <16 x i8>, ptr %b, align 16
161  %2 = tail call <16 x i8> @llvm.mips.div.u.b(<16 x i8> %0, <16 x i8> %1)
162  store <16 x i8> %2, ptr %c, align 16
163  ret void
164}
165
166declare <8 x i16> @llvm.mips.div.u.h(<8 x i16>, <8 x i16>)
167define void @udiv_v8u16_builtin(ptr %a, ptr %b, ptr %c) {
168; P5600-LABEL: udiv_v8u16_builtin:
169; P5600:       # %bb.0: # %entry
170; P5600-NEXT:    ld.h $w0, 0($4)
171; P5600-NEXT:    ld.h $w1, 0($5)
172; P5600-NEXT:    div_u.h $w0, $w0, $w1
173; P5600-NEXT:    st.h $w0, 0($6)
174; P5600-NEXT:    jr $ra
175; P5600-NEXT:    nop
176entry:
177  %0 = load <8 x i16>, ptr %a, align 16
178  %1 = load <8 x i16>, ptr %b, align 16
179  %2 = tail call <8 x i16> @llvm.mips.div.u.h(<8 x i16> %0, <8 x i16> %1)
180  store <8 x i16> %2, ptr %c, align 16
181  ret void
182}
183
184declare <4 x i32> @llvm.mips.div.u.w(<4 x i32>, <4 x i32>)
185define void @udiv_v4u32_builtin(ptr %a, ptr %b, ptr %c) {
186; P5600-LABEL: udiv_v4u32_builtin:
187; P5600:       # %bb.0: # %entry
188; P5600-NEXT:    ld.w $w0, 0($4)
189; P5600-NEXT:    ld.w $w1, 0($5)
190; P5600-NEXT:    div_u.w $w0, $w0, $w1
191; P5600-NEXT:    st.w $w0, 0($6)
192; P5600-NEXT:    jr $ra
193; P5600-NEXT:    nop
194entry:
195  %0 = load <4 x i32>, ptr %a, align 16
196  %1 = load <4 x i32>, ptr %b, align 16
197  %2 = tail call <4 x i32> @llvm.mips.div.u.w(<4 x i32> %0, <4 x i32> %1)
198  store <4 x i32> %2, ptr %c, align 16
199  ret void
200}
201
202declare <2 x i64> @llvm.mips.div.u.d(<2 x i64>, <2 x i64>)
203define void @udiv_v2u64_builtin(ptr %a, ptr %b, ptr %c) {
204; P5600-LABEL: udiv_v2u64_builtin:
205; P5600:       # %bb.0: # %entry
206; P5600-NEXT:    ld.d $w0, 0($4)
207; P5600-NEXT:    ld.d $w1, 0($5)
208; P5600-NEXT:    div_u.d $w0, $w0, $w1
209; P5600-NEXT:    st.d $w0, 0($6)
210; P5600-NEXT:    jr $ra
211; P5600-NEXT:    nop
212entry:
213  %0 = load <2 x i64>, ptr %a, align 16
214  %1 = load <2 x i64>, ptr %b, align 16
215  %2 = tail call <2 x i64> @llvm.mips.div.u.d(<2 x i64> %0, <2 x i64> %1)
216  store <2 x i64> %2, ptr %c, align 16
217  ret void
218}
219
220declare <16 x i8> @llvm.mips.mod.u.b(<16 x i8>, <16 x i8>)
221define void @umod_v16u8_builtin(ptr %a, ptr %b, ptr %c) {
222; P5600-LABEL: umod_v16u8_builtin:
223; P5600:       # %bb.0: # %entry
224; P5600-NEXT:    ld.b $w0, 0($4)
225; P5600-NEXT:    ld.b $w1, 0($5)
226; P5600-NEXT:    mod_u.b $w0, $w0, $w1
227; P5600-NEXT:    st.b $w0, 0($6)
228; P5600-NEXT:    jr $ra
229; P5600-NEXT:    nop
230entry:
231  %0 = load <16 x i8>, ptr %a, align 16
232  %1 = load <16 x i8>, ptr %b, align 16
233  %2 = tail call <16 x i8> @llvm.mips.mod.u.b(<16 x i8> %0, <16 x i8> %1)
234  store <16 x i8> %2, ptr %c, align 16
235  ret void
236}
237
238declare <8 x i16> @llvm.mips.mod.u.h(<8 x i16>, <8 x i16>)
239define void @umod_v8u16_builtin(ptr %a, ptr %b, ptr %c) {
240; P5600-LABEL: umod_v8u16_builtin:
241; P5600:       # %bb.0: # %entry
242; P5600-NEXT:    ld.h $w0, 0($4)
243; P5600-NEXT:    ld.h $w1, 0($5)
244; P5600-NEXT:    mod_u.h $w0, $w0, $w1
245; P5600-NEXT:    st.h $w0, 0($6)
246; P5600-NEXT:    jr $ra
247; P5600-NEXT:    nop
248entry:
249  %0 = load <8 x i16>, ptr %a, align 16
250  %1 = load <8 x i16>, ptr %b, align 16
251  %2 = tail call <8 x i16> @llvm.mips.mod.u.h(<8 x i16> %0, <8 x i16> %1)
252  store <8 x i16> %2, ptr %c, align 16
253  ret void
254}
255
256declare <4 x i32> @llvm.mips.mod.u.w(<4 x i32>, <4 x i32>)
257define void @umod_v4u32_builtin(ptr %a, ptr %b, ptr %c) {
258; P5600-LABEL: umod_v4u32_builtin:
259; P5600:       # %bb.0: # %entry
260; P5600-NEXT:    ld.w $w0, 0($4)
261; P5600-NEXT:    ld.w $w1, 0($5)
262; P5600-NEXT:    mod_u.w $w0, $w0, $w1
263; P5600-NEXT:    st.w $w0, 0($6)
264; P5600-NEXT:    jr $ra
265; P5600-NEXT:    nop
266entry:
267  %0 = load <4 x i32>, ptr %a, align 16
268  %1 = load <4 x i32>, ptr %b, align 16
269  %2 = tail call <4 x i32> @llvm.mips.mod.u.w(<4 x i32> %0, <4 x i32> %1)
270  store <4 x i32> %2, ptr %c, align 16
271  ret void
272}
273
274declare <2 x i64> @llvm.mips.mod.u.d(<2 x i64>, <2 x i64>)
275define void @umod_v2u64_builtin(ptr %a, ptr %b, ptr %c) {
276; P5600-LABEL: umod_v2u64_builtin:
277; P5600:       # %bb.0: # %entry
278; P5600-NEXT:    ld.d $w0, 0($4)
279; P5600-NEXT:    ld.d $w1, 0($5)
280; P5600-NEXT:    mod_u.d $w0, $w0, $w1
281; P5600-NEXT:    st.d $w0, 0($6)
282; P5600-NEXT:    jr $ra
283; P5600-NEXT:    nop
284entry:
285  %0 = load <2 x i64>, ptr %a, align 16
286  %1 = load <2 x i64>, ptr %b, align 16
287  %2 = tail call <2 x i64> @llvm.mips.mod.u.d(<2 x i64> %0, <2 x i64> %1)
288  store <2 x i64> %2, ptr %c, align 16
289  ret void
290}
291