1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
3
4declare <4 x float> @llvm.mips.fadd.w(<4 x float>, <4 x float>)
5define void @fadd_v4f32_builtin(ptr %a, ptr %b, ptr %c) {
6; P5600-LABEL: fadd_v4f32_builtin:
7; P5600:       # %bb.0: # %entry
8; P5600-NEXT:    ld.w $w0, 0($4)
9; P5600-NEXT:    ld.w $w1, 0($5)
10; P5600-NEXT:    fadd.w $w0, $w0, $w1
11; P5600-NEXT:    st.w $w0, 0($6)
12; P5600-NEXT:    jr $ra
13; P5600-NEXT:    nop
14entry:
15  %0 = load <4 x float>, ptr %a, align 16
16  %1 = load <4 x float>, ptr %b, align 16
17  %2 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %1)
18  store <4 x float> %2, ptr %c, align 16
19  ret void
20}
21
22declare <2 x double> @llvm.mips.fadd.d(<2 x double>, <2 x double>)
23define void @fadd_v2f64_builtin(ptr %a, ptr %b, ptr %c) {
24; P5600-LABEL: fadd_v2f64_builtin:
25; P5600:       # %bb.0: # %entry
26; P5600-NEXT:    ld.d $w0, 0($4)
27; P5600-NEXT:    ld.d $w1, 0($5)
28; P5600-NEXT:    fadd.d $w0, $w0, $w1
29; P5600-NEXT:    st.d $w0, 0($6)
30; P5600-NEXT:    jr $ra
31; P5600-NEXT:    nop
32entry:
33  %0 = load <2 x double>, ptr %a, align 16
34  %1 = load <2 x double>, ptr %b, align 16
35  %2 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %1)
36  store <2 x double> %2, ptr %c, align 16
37  ret void
38}
39
40declare <4 x float> @llvm.mips.fsub.w(<4 x float>, <4 x float>)
41define void @fsub_v4f32_builtin(ptr %a, ptr %b, ptr %c) {
42; P5600-LABEL: fsub_v4f32_builtin:
43; P5600:       # %bb.0: # %entry
44; P5600-NEXT:    ld.w $w0, 0($4)
45; P5600-NEXT:    ld.w $w1, 0($5)
46; P5600-NEXT:    fsub.w $w0, $w0, $w1
47; P5600-NEXT:    st.w $w0, 0($6)
48; P5600-NEXT:    jr $ra
49; P5600-NEXT:    nop
50entry:
51  %0 = load <4 x float>, ptr %a, align 16
52  %1 = load <4 x float>, ptr %b, align 16
53  %2 = tail call <4 x float> @llvm.mips.fsub.w(<4 x float> %0, <4 x float> %1)
54  store <4 x float> %2, ptr %c, align 16
55  ret void
56}
57
58declare <2 x double> @llvm.mips.fsub.d(<2 x double>, <2 x double>)
59define void @fsub_v2f64_builtin(ptr %a, ptr %b, ptr %c) {
60; P5600-LABEL: fsub_v2f64_builtin:
61; P5600:       # %bb.0: # %entry
62; P5600-NEXT:    ld.d $w0, 0($4)
63; P5600-NEXT:    ld.d $w1, 0($5)
64; P5600-NEXT:    fsub.d $w0, $w0, $w1
65; P5600-NEXT:    st.d $w0, 0($6)
66; P5600-NEXT:    jr $ra
67; P5600-NEXT:    nop
68entry:
69  %0 = load <2 x double>, ptr %a, align 16
70  %1 = load <2 x double>, ptr %b, align 16
71  %2 = tail call <2 x double> @llvm.mips.fsub.d(<2 x double> %0, <2 x double> %1)
72  store <2 x double> %2, ptr %c, align 16
73  ret void
74}
75
76declare <4 x float> @llvm.mips.fmul.w(<4 x float>, <4 x float>)
77define void @fmul_v4f32_builtin(ptr %a, ptr %b, ptr %c) {
78; P5600-LABEL: fmul_v4f32_builtin:
79; P5600:       # %bb.0: # %entry
80; P5600-NEXT:    ld.w $w0, 0($4)
81; P5600-NEXT:    ld.w $w1, 0($5)
82; P5600-NEXT:    fmul.w $w0, $w0, $w1
83; P5600-NEXT:    st.w $w0, 0($6)
84; P5600-NEXT:    jr $ra
85; P5600-NEXT:    nop
86entry:
87  %0 = load <4 x float>, ptr %a, align 16
88  %1 = load <4 x float>, ptr %b, align 16
89  %2 = tail call <4 x float> @llvm.mips.fmul.w(<4 x float> %0, <4 x float> %1)
90  store <4 x float> %2, ptr %c, align 16
91  ret void
92}
93
94declare <2 x double> @llvm.mips.fmul.d(<2 x double>, <2 x double>)
95define void @fmul_v2f64_builtin(ptr %a, ptr %b, ptr %c) {
96; P5600-LABEL: fmul_v2f64_builtin:
97; P5600:       # %bb.0: # %entry
98; P5600-NEXT:    ld.d $w0, 0($4)
99; P5600-NEXT:    ld.d $w1, 0($5)
100; P5600-NEXT:    fmul.d $w0, $w0, $w1
101; P5600-NEXT:    st.d $w0, 0($6)
102; P5600-NEXT:    jr $ra
103; P5600-NEXT:    nop
104entry:
105  %0 = load <2 x double>, ptr %a, align 16
106  %1 = load <2 x double>, ptr %b, align 16
107  %2 = tail call <2 x double> @llvm.mips.fmul.d(<2 x double> %0, <2 x double> %1)
108  store <2 x double> %2, ptr %c, align 16
109  ret void
110}
111
112declare <4 x float> @llvm.mips.fdiv.w(<4 x float>, <4 x float>)
113define void @fdiv_v4f32_builtin(ptr %a, ptr %b, ptr %c) {
114; P5600-LABEL: fdiv_v4f32_builtin:
115; P5600:       # %bb.0: # %entry
116; P5600-NEXT:    ld.w $w0, 0($4)
117; P5600-NEXT:    ld.w $w1, 0($5)
118; P5600-NEXT:    fdiv.w $w0, $w0, $w1
119; P5600-NEXT:    st.w $w0, 0($6)
120; P5600-NEXT:    jr $ra
121; P5600-NEXT:    nop
122entry:
123  %0 = load <4 x float>, ptr %a, align 16
124  %1 = load <4 x float>, ptr %b, align 16
125  %2 = tail call <4 x float> @llvm.mips.fdiv.w(<4 x float> %0, <4 x float> %1)
126  store <4 x float> %2, ptr %c, align 16
127  ret void
128}
129
130declare <2 x double> @llvm.mips.fdiv.d(<2 x double>, <2 x double>)
131define void @fdiv_v2f64_builtin(ptr %a, ptr %b, ptr %c) {
132; P5600-LABEL: fdiv_v2f64_builtin:
133; P5600:       # %bb.0: # %entry
134; P5600-NEXT:    ld.d $w0, 0($4)
135; P5600-NEXT:    ld.d $w1, 0($5)
136; P5600-NEXT:    fdiv.d $w0, $w0, $w1
137; P5600-NEXT:    st.d $w0, 0($6)
138; P5600-NEXT:    jr $ra
139; P5600-NEXT:    nop
140entry:
141  %0 = load <2 x double>, ptr %a, align 16
142  %1 = load <2 x double>, ptr %b, align 16
143  %2 = tail call <2 x double> @llvm.mips.fdiv.d(<2 x double> %0, <2 x double> %1)
144  store <2 x double> %2, ptr %c, align 16
145  ret void
146}
147