1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 3--- | 4 5 define void @load1_s8_to_zextLoad1_s32(ptr %px) {entry: ret void} 6 define void @load2_s16_to_zextLoad2_s32(ptr %px) {entry: ret void} 7 define void @load1_s8_to_zextLoad1_s16(ptr %px) {entry: ret void} 8 define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(ptr %px) {entry: ret void} 9 define void @load4_s32_to_zextLoad4_s64(ptr %px) {entry: ret void} 10 define void @load1_s8_to_sextLoad1_s32(ptr %px) {entry: ret void} 11 define void @load2_s16_to_sextLoad2_s32(ptr %px) {entry: ret void} 12 define void @load1_s8_to_sextLoad1_s16(ptr %px) {entry: ret void} 13 define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(ptr %px) {entry: ret void} 14 define void @load4_s32_to_sextLoad4_s64(ptr %px) {entry: ret void} 15 16... 17--- 18name: load1_s8_to_zextLoad1_s32 19alignment: 4 20tracksRegLiveness: true 21body: | 22 bb.1.entry: 23 liveins: $a0 24 25 ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s32 26 ; MIPS32: liveins: $a0 27 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 28 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px) 29 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32) 30 ; MIPS32: RetRA implicit $v0 31 %0:_(p0) = COPY $a0 32 %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px) 33 $v0 = COPY %2(s32) 34 RetRA implicit $v0 35 36... 37--- 38name: load2_s16_to_zextLoad2_s32 39alignment: 4 40tracksRegLiveness: true 41body: | 42 bb.1.entry: 43 liveins: $a0 44 45 ; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s32 46 ; MIPS32: liveins: $a0 47 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 48 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px) 49 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32) 50 ; MIPS32: RetRA implicit $v0 51 %0:_(p0) = COPY $a0 52 %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.px) 53 $v0 = COPY %2(s32) 54 RetRA implicit $v0 55 56... 57--- 58name: load1_s8_to_zextLoad1_s16 59alignment: 4 60tracksRegLiveness: true 61body: | 62 bb.1.entry: 63 liveins: $a0 64 65 ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16 66 ; MIPS32: liveins: $a0 67 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 68 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px) 69 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32) 70 ; MIPS32: RetRA implicit $v0 71 %0:_(p0) = COPY $a0 72 %2:_(s16) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px) 73 %3:_(s32) = G_ANYEXT %2(s16) 74 $v0 = COPY %3(s32) 75 RetRA implicit $v0 76 77... 78--- 79name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32 80alignment: 4 81tracksRegLiveness: true 82body: | 83 bb.1.entry: 84 liveins: $a0 85 86 ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32 87 ; MIPS32: liveins: $a0 88 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 89 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px) 90 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32) 91 ; MIPS32: RetRA implicit $v0 92 %0:_(p0) = COPY $a0 93 %3:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px) 94 $v0 = COPY %3(s32) 95 RetRA implicit $v0 96 97... 98--- 99name: load4_s32_to_zextLoad4_s64 100alignment: 4 101tracksRegLiveness: true 102body: | 103 bb.1.entry: 104 liveins: $a0 105 106 ; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64 107 ; MIPS32: liveins: $a0 108 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 109 ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px) 110 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 111 ; MIPS32: $v0 = COPY [[LOAD]](s32) 112 ; MIPS32: $v1 = COPY [[C]](s32) 113 ; MIPS32: RetRA implicit $v0, implicit $v1 114 %0:_(p0) = COPY $a0 115 %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s32) from %ir.px) 116 %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64) 117 $v0 = COPY %3(s32) 118 $v1 = COPY %4(s32) 119 RetRA implicit $v0, implicit $v1 120 121... 122--- 123name: load1_s8_to_sextLoad1_s32 124alignment: 4 125tracksRegLiveness: true 126body: | 127 bb.1.entry: 128 liveins: $a0 129 130 ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32 131 ; MIPS32: liveins: $a0 132 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 133 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px) 134 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32) 135 ; MIPS32: RetRA implicit $v0 136 %0:_(p0) = COPY $a0 137 %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px) 138 $v0 = COPY %2(s32) 139 RetRA implicit $v0 140 141... 142--- 143name: load2_s16_to_sextLoad2_s32 144alignment: 4 145tracksRegLiveness: true 146body: | 147 bb.1.entry: 148 liveins: $a0 149 150 ; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s32 151 ; MIPS32: liveins: $a0 152 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 153 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px) 154 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32) 155 ; MIPS32: RetRA implicit $v0 156 %0:_(p0) = COPY $a0 157 %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16) from %ir.px) 158 $v0 = COPY %2(s32) 159 RetRA implicit $v0 160 161... 162--- 163name: load1_s8_to_sextLoad1_s16 164alignment: 4 165tracksRegLiveness: true 166body: | 167 bb.1.entry: 168 liveins: $a0 169 170 ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16 171 ; MIPS32: liveins: $a0 172 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 173 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px) 174 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32) 175 ; MIPS32: RetRA implicit $v0 176 %0:_(p0) = COPY $a0 177 %2:_(s16) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px) 178 %3:_(s32) = G_ANYEXT %2(s16) 179 $v0 = COPY %3(s32) 180 RetRA implicit $v0 181 182... 183--- 184name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32 185alignment: 4 186tracksRegLiveness: true 187body: | 188 bb.1.entry: 189 liveins: $a0 190 191 ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32 192 ; MIPS32: liveins: $a0 193 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 194 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px) 195 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32) 196 ; MIPS32: RetRA implicit $v0 197 %0:_(p0) = COPY $a0 198 %3:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px) 199 $v0 = COPY %3(s32) 200 RetRA implicit $v0 201 202... 203--- 204name: load4_s32_to_sextLoad4_s64 205alignment: 4 206tracksRegLiveness: true 207body: | 208 bb.1.entry: 209 liveins: $a0 210 211 ; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64 212 ; MIPS32: liveins: $a0 213 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 214 ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px) 215 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 216 ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[C]](s32) 217 ; MIPS32: $v0 = COPY [[LOAD]](s32) 218 ; MIPS32: $v1 = COPY [[ASHR]](s32) 219 ; MIPS32: RetRA implicit $v0, implicit $v1 220 %0:_(p0) = COPY $a0 221 %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s32) from %ir.px) 222 %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64) 223 $v0 = COPY %3(s32) 224 $v1 = COPY %4(s32) 225 RetRA implicit $v0, implicit $v1 226 227... 228