xref: /llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div_vec_builtin.mir (revision 60442f0d442723a487528bdd8b48b24657a025e8) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
3--- |
4
5  declare <16 x i8> @llvm.mips.div.s.b(<16 x i8>, <16 x i8>)
6  define void @sdiv_v16i8_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
7
8  declare <8 x i16> @llvm.mips.div.s.h(<8 x i16>, <8 x i16>)
9  define void @sdiv_v8i16_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
10
11  declare <4 x i32> @llvm.mips.div.s.w(<4 x i32>, <4 x i32>)
12  define void @sdiv_v4i32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
13
14  declare <2 x i64> @llvm.mips.div.s.d(<2 x i64>, <2 x i64>)
15  define void @sdiv_v2i64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
16
17  declare <16 x i8> @llvm.mips.mod.s.b(<16 x i8>, <16 x i8>)
18  define void @smod_v16i8_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
19
20  declare <8 x i16> @llvm.mips.mod.s.h(<8 x i16>, <8 x i16>)
21  define void @smod_v8i16_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
22
23  declare <4 x i32> @llvm.mips.mod.s.w(<4 x i32>, <4 x i32>)
24  define void @smod_v4i32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
25
26  declare <2 x i64> @llvm.mips.mod.s.d(<2 x i64>, <2 x i64>)
27  define void @smod_v2i64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
28
29  declare <16 x i8> @llvm.mips.div.u.b(<16 x i8>, <16 x i8>)
30  define void @udiv_v16i8_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
31
32  declare <8 x i16> @llvm.mips.div.u.h(<8 x i16>, <8 x i16>)
33  define void @udiv_v8i16_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
34
35  declare <4 x i32> @llvm.mips.div.u.w(<4 x i32>, <4 x i32>)
36  define void @udiv_v4i32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
37
38  declare <2 x i64> @llvm.mips.div.u.d(<2 x i64>, <2 x i64>)
39  define void @udiv_v2i64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
40
41  declare <16 x i8> @llvm.mips.mod.u.b(<16 x i8>, <16 x i8>)
42  define void @umod_v16i8_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
43
44  declare <8 x i16> @llvm.mips.mod.u.h(<8 x i16>, <8 x i16>)
45  define void @umod_v8i16_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
46
47  declare <4 x i32> @llvm.mips.mod.u.w(<4 x i32>, <4 x i32>)
48  define void @umod_v4i32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
49
50  declare <2 x i64> @llvm.mips.mod.u.d(<2 x i64>, <2 x i64>)
51  define void @umod_v2i64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
52
53...
54---
55name:            sdiv_v16i8_builtin
56alignment:       4
57tracksRegLiveness: true
58body:             |
59  bb.1.entry:
60    liveins: $a0, $a1, $a2
61
62    ; P5600-LABEL: name: sdiv_v16i8_builtin
63    ; P5600: liveins: $a0, $a1, $a2
64    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
65    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
66    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
67    ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
68    ; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
69    ; P5600: [[SDIV:%[0-9]+]]:_(<16 x s8>) = G_SDIV [[LOAD]], [[LOAD1]]
70    ; P5600: G_STORE [[SDIV]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
71    ; P5600: RetRA
72    %0:_(p0) = COPY $a0
73    %1:_(p0) = COPY $a1
74    %2:_(p0) = COPY $a2
75    %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
76    %4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
77    %5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.div.s.b), %3(<16 x s8>), %4(<16 x s8>)
78    G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)
79    RetRA
80
81...
82---
83name:            sdiv_v8i16_builtin
84alignment:       4
85tracksRegLiveness: true
86body:             |
87  bb.1.entry:
88    liveins: $a0, $a1, $a2
89
90    ; P5600-LABEL: name: sdiv_v8i16_builtin
91    ; P5600: liveins: $a0, $a1, $a2
92    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
93    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
94    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
95    ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
96    ; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
97    ; P5600: [[SDIV:%[0-9]+]]:_(<8 x s16>) = G_SDIV [[LOAD]], [[LOAD1]]
98    ; P5600: G_STORE [[SDIV]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
99    ; P5600: RetRA
100    %0:_(p0) = COPY $a0
101    %1:_(p0) = COPY $a1
102    %2:_(p0) = COPY $a2
103    %3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
104    %4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
105    %5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.div.s.h), %3(<8 x s16>), %4(<8 x s16>)
106    G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)
107    RetRA
108
109...
110---
111name:            sdiv_v4i32_builtin
112alignment:       4
113tracksRegLiveness: true
114body:             |
115  bb.1.entry:
116    liveins: $a0, $a1, $a2
117
118    ; P5600-LABEL: name: sdiv_v4i32_builtin
119    ; P5600: liveins: $a0, $a1, $a2
120    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
121    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
122    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
123    ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
124    ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
125    ; P5600: [[SDIV:%[0-9]+]]:_(<4 x s32>) = G_SDIV [[LOAD]], [[LOAD1]]
126    ; P5600: G_STORE [[SDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
127    ; P5600: RetRA
128    %0:_(p0) = COPY $a0
129    %1:_(p0) = COPY $a1
130    %2:_(p0) = COPY $a2
131    %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
132    %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
133    %5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.div.s.w), %3(<4 x s32>), %4(<4 x s32>)
134    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
135    RetRA
136
137...
138---
139name:            sdiv_v2i64_builtin
140alignment:       4
141tracksRegLiveness: true
142body:             |
143  bb.1.entry:
144    liveins: $a0, $a1, $a2
145
146    ; P5600-LABEL: name: sdiv_v2i64_builtin
147    ; P5600: liveins: $a0, $a1, $a2
148    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
149    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
150    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
151    ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
152    ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
153    ; P5600: [[SDIV:%[0-9]+]]:_(<2 x s64>) = G_SDIV [[LOAD]], [[LOAD1]]
154    ; P5600: G_STORE [[SDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
155    ; P5600: RetRA
156    %0:_(p0) = COPY $a0
157    %1:_(p0) = COPY $a1
158    %2:_(p0) = COPY $a2
159    %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
160    %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
161    %5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.div.s.d), %3(<2 x s64>), %4(<2 x s64>)
162    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
163    RetRA
164
165...
166---
167name:            smod_v16i8_builtin
168alignment:       4
169tracksRegLiveness: true
170body:             |
171  bb.1.entry:
172    liveins: $a0, $a1, $a2
173
174    ; P5600-LABEL: name: smod_v16i8_builtin
175    ; P5600: liveins: $a0, $a1, $a2
176    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
177    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
178    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
179    ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
180    ; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
181    ; P5600: [[SREM:%[0-9]+]]:_(<16 x s8>) = G_SREM [[LOAD]], [[LOAD1]]
182    ; P5600: G_STORE [[SREM]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
183    ; P5600: RetRA
184    %0:_(p0) = COPY $a0
185    %1:_(p0) = COPY $a1
186    %2:_(p0) = COPY $a2
187    %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
188    %4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
189    %5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.mod.s.b), %3(<16 x s8>), %4(<16 x s8>)
190    G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)
191    RetRA
192
193...
194---
195name:            smod_v8i16_builtin
196alignment:       4
197tracksRegLiveness: true
198body:             |
199  bb.1.entry:
200    liveins: $a0, $a1, $a2
201
202    ; P5600-LABEL: name: smod_v8i16_builtin
203    ; P5600: liveins: $a0, $a1, $a2
204    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
205    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
206    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
207    ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
208    ; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
209    ; P5600: [[SREM:%[0-9]+]]:_(<8 x s16>) = G_SREM [[LOAD]], [[LOAD1]]
210    ; P5600: G_STORE [[SREM]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
211    ; P5600: RetRA
212    %0:_(p0) = COPY $a0
213    %1:_(p0) = COPY $a1
214    %2:_(p0) = COPY $a2
215    %3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
216    %4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
217    %5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.mod.s.h), %3(<8 x s16>), %4(<8 x s16>)
218    G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)
219    RetRA
220
221...
222---
223name:            smod_v4i32_builtin
224alignment:       4
225tracksRegLiveness: true
226body:             |
227  bb.1.entry:
228    liveins: $a0, $a1, $a2
229
230    ; P5600-LABEL: name: smod_v4i32_builtin
231    ; P5600: liveins: $a0, $a1, $a2
232    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
233    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
234    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
235    ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
236    ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
237    ; P5600: [[SREM:%[0-9]+]]:_(<4 x s32>) = G_SREM [[LOAD]], [[LOAD1]]
238    ; P5600: G_STORE [[SREM]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
239    ; P5600: RetRA
240    %0:_(p0) = COPY $a0
241    %1:_(p0) = COPY $a1
242    %2:_(p0) = COPY $a2
243    %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
244    %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
245    %5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.mod.s.w), %3(<4 x s32>), %4(<4 x s32>)
246    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
247    RetRA
248
249...
250---
251name:            smod_v2i64_builtin
252alignment:       4
253tracksRegLiveness: true
254body:             |
255  bb.1.entry:
256    liveins: $a0, $a1, $a2
257
258    ; P5600-LABEL: name: smod_v2i64_builtin
259    ; P5600: liveins: $a0, $a1, $a2
260    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
261    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
262    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
263    ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
264    ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
265    ; P5600: [[SREM:%[0-9]+]]:_(<2 x s64>) = G_SREM [[LOAD]], [[LOAD1]]
266    ; P5600: G_STORE [[SREM]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
267    ; P5600: RetRA
268    %0:_(p0) = COPY $a0
269    %1:_(p0) = COPY $a1
270    %2:_(p0) = COPY $a2
271    %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
272    %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
273    %5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.mod.s.d), %3(<2 x s64>), %4(<2 x s64>)
274    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
275    RetRA
276
277...
278---
279name:            udiv_v16i8_builtin
280alignment:       4
281tracksRegLiveness: true
282body:             |
283  bb.1.entry:
284    liveins: $a0, $a1, $a2
285
286    ; P5600-LABEL: name: udiv_v16i8_builtin
287    ; P5600: liveins: $a0, $a1, $a2
288    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
289    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
290    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
291    ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
292    ; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
293    ; P5600: [[UDIV:%[0-9]+]]:_(<16 x s8>) = G_UDIV [[LOAD]], [[LOAD1]]
294    ; P5600: G_STORE [[UDIV]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
295    ; P5600: RetRA
296    %0:_(p0) = COPY $a0
297    %1:_(p0) = COPY $a1
298    %2:_(p0) = COPY $a2
299    %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
300    %4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
301    %5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.div.u.b), %3(<16 x s8>), %4(<16 x s8>)
302    G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)
303    RetRA
304
305...
306---
307name:            udiv_v8i16_builtin
308alignment:       4
309tracksRegLiveness: true
310body:             |
311  bb.1.entry:
312    liveins: $a0, $a1, $a2
313
314    ; P5600-LABEL: name: udiv_v8i16_builtin
315    ; P5600: liveins: $a0, $a1, $a2
316    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
317    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
318    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
319    ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
320    ; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
321    ; P5600: [[UDIV:%[0-9]+]]:_(<8 x s16>) = G_UDIV [[LOAD]], [[LOAD1]]
322    ; P5600: G_STORE [[UDIV]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
323    ; P5600: RetRA
324    %0:_(p0) = COPY $a0
325    %1:_(p0) = COPY $a1
326    %2:_(p0) = COPY $a2
327    %3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
328    %4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
329    %5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.div.u.h), %3(<8 x s16>), %4(<8 x s16>)
330    G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)
331    RetRA
332
333...
334---
335name:            udiv_v4i32_builtin
336alignment:       4
337tracksRegLiveness: true
338body:             |
339  bb.1.entry:
340    liveins: $a0, $a1, $a2
341
342    ; P5600-LABEL: name: udiv_v4i32_builtin
343    ; P5600: liveins: $a0, $a1, $a2
344    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
345    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
346    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
347    ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
348    ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
349    ; P5600: [[UDIV:%[0-9]+]]:_(<4 x s32>) = G_UDIV [[LOAD]], [[LOAD1]]
350    ; P5600: G_STORE [[UDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
351    ; P5600: RetRA
352    %0:_(p0) = COPY $a0
353    %1:_(p0) = COPY $a1
354    %2:_(p0) = COPY $a2
355    %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
356    %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
357    %5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.div.u.w), %3(<4 x s32>), %4(<4 x s32>)
358    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
359    RetRA
360
361...
362---
363name:            udiv_v2i64_builtin
364alignment:       4
365tracksRegLiveness: true
366body:             |
367  bb.1.entry:
368    liveins: $a0, $a1, $a2
369
370    ; P5600-LABEL: name: udiv_v2i64_builtin
371    ; P5600: liveins: $a0, $a1, $a2
372    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
373    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
374    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
375    ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
376    ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
377    ; P5600: [[UDIV:%[0-9]+]]:_(<2 x s64>) = G_UDIV [[LOAD]], [[LOAD1]]
378    ; P5600: G_STORE [[UDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
379    ; P5600: RetRA
380    %0:_(p0) = COPY $a0
381    %1:_(p0) = COPY $a1
382    %2:_(p0) = COPY $a2
383    %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
384    %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
385    %5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.div.u.d), %3(<2 x s64>), %4(<2 x s64>)
386    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
387    RetRA
388
389...
390---
391name:            umod_v16i8_builtin
392alignment:       4
393tracksRegLiveness: true
394body:             |
395  bb.1.entry:
396    liveins: $a0, $a1, $a2
397
398    ; P5600-LABEL: name: umod_v16i8_builtin
399    ; P5600: liveins: $a0, $a1, $a2
400    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
401    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
402    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
403    ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
404    ; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
405    ; P5600: [[UREM:%[0-9]+]]:_(<16 x s8>) = G_UREM [[LOAD]], [[LOAD1]]
406    ; P5600: G_STORE [[UREM]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
407    ; P5600: RetRA
408    %0:_(p0) = COPY $a0
409    %1:_(p0) = COPY $a1
410    %2:_(p0) = COPY $a2
411    %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
412    %4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
413    %5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.mod.u.b), %3(<16 x s8>), %4(<16 x s8>)
414    G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)
415    RetRA
416
417...
418---
419name:            umod_v8i16_builtin
420alignment:       4
421tracksRegLiveness: true
422body:             |
423  bb.1.entry:
424    liveins: $a0, $a1, $a2
425
426    ; P5600-LABEL: name: umod_v8i16_builtin
427    ; P5600: liveins: $a0, $a1, $a2
428    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
429    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
430    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
431    ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
432    ; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
433    ; P5600: [[UREM:%[0-9]+]]:_(<8 x s16>) = G_UREM [[LOAD]], [[LOAD1]]
434    ; P5600: G_STORE [[UREM]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
435    ; P5600: RetRA
436    %0:_(p0) = COPY $a0
437    %1:_(p0) = COPY $a1
438    %2:_(p0) = COPY $a2
439    %3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
440    %4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
441    %5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.mod.u.h), %3(<8 x s16>), %4(<8 x s16>)
442    G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)
443    RetRA
444
445...
446---
447name:            umod_v4i32_builtin
448alignment:       4
449tracksRegLiveness: true
450body:             |
451  bb.1.entry:
452    liveins: $a0, $a1, $a2
453
454    ; P5600-LABEL: name: umod_v4i32_builtin
455    ; P5600: liveins: $a0, $a1, $a2
456    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
457    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
458    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
459    ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
460    ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
461    ; P5600: [[UREM:%[0-9]+]]:_(<4 x s32>) = G_UREM [[LOAD]], [[LOAD1]]
462    ; P5600: G_STORE [[UREM]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
463    ; P5600: RetRA
464    %0:_(p0) = COPY $a0
465    %1:_(p0) = COPY $a1
466    %2:_(p0) = COPY $a2
467    %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
468    %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
469    %5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.mod.u.w), %3(<4 x s32>), %4(<4 x s32>)
470    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
471    RetRA
472
473...
474---
475name:            umod_v2i64_builtin
476alignment:       4
477tracksRegLiveness: true
478body:             |
479  bb.1.entry:
480    liveins: $a0, $a1, $a2
481
482    ; P5600-LABEL: name: umod_v2i64_builtin
483    ; P5600: liveins: $a0, $a1, $a2
484    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
485    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
486    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
487    ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
488    ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
489    ; P5600: [[UREM:%[0-9]+]]:_(<2 x s64>) = G_UREM [[LOAD]], [[LOAD1]]
490    ; P5600: G_STORE [[UREM]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
491    ; P5600: RetRA
492    %0:_(p0) = COPY $a0
493    %1:_(p0) = COPY $a1
494    %2:_(p0) = COPY $a2
495    %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
496    %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
497    %5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.mod.u.d), %3(<2 x s64>), %4(<2 x s64>)
498    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
499    RetRA
500
501...
502