1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600 3--- | 4 5 declare <16 x i8> @llvm.mips.mulv.b(<16 x i8>, <16 x i8>) 6 define void @mul_v16i8_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void } 7 8 declare <8 x i16> @llvm.mips.mulv.h(<8 x i16>, <8 x i16>) 9 define void @mul_v8i16_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void } 10 11 declare <4 x i32> @llvm.mips.mulv.w(<4 x i32>, <4 x i32>) 12 define void @mul_v4i32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void } 13 14 declare <2 x i64> @llvm.mips.mulv.d(<2 x i64>, <2 x i64>) 15 define void @mul_v2i64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void } 16 17... 18--- 19name: mul_v16i8_builtin 20alignment: 4 21tracksRegLiveness: true 22body: | 23 bb.1.entry: 24 liveins: $a0, $a1, $a2 25 26 ; P5600-LABEL: name: mul_v16i8_builtin 27 ; P5600: liveins: $a0, $a1, $a2 28 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 29 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1 30 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2 31 ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a) 32 ; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b) 33 ; P5600: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[LOAD]], [[LOAD1]] 34 ; P5600: G_STORE [[MUL]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c) 35 ; P5600: RetRA 36 %0:_(p0) = COPY $a0 37 %1:_(p0) = COPY $a1 38 %2:_(p0) = COPY $a2 39 %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a) 40 %4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b) 41 %5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.mulv.b), %3(<16 x s8>), %4(<16 x s8>) 42 G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c) 43 RetRA 44 45... 46--- 47name: mul_v8i16_builtin 48alignment: 4 49tracksRegLiveness: true 50body: | 51 bb.1.entry: 52 liveins: $a0, $a1, $a2 53 54 ; P5600-LABEL: name: mul_v8i16_builtin 55 ; P5600: liveins: $a0, $a1, $a2 56 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 57 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1 58 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2 59 ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a) 60 ; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b) 61 ; P5600: [[MUL:%[0-9]+]]:_(<8 x s16>) = G_MUL [[LOAD]], [[LOAD1]] 62 ; P5600: G_STORE [[MUL]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c) 63 ; P5600: RetRA 64 %0:_(p0) = COPY $a0 65 %1:_(p0) = COPY $a1 66 %2:_(p0) = COPY $a2 67 %3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a) 68 %4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b) 69 %5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.mulv.h), %3(<8 x s16>), %4(<8 x s16>) 70 G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c) 71 RetRA 72 73... 74--- 75name: mul_v4i32_builtin 76alignment: 4 77tracksRegLiveness: true 78body: | 79 bb.1.entry: 80 liveins: $a0, $a1, $a2 81 82 ; P5600-LABEL: name: mul_v4i32_builtin 83 ; P5600: liveins: $a0, $a1, $a2 84 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 85 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1 86 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2 87 ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a) 88 ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b) 89 ; P5600: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[LOAD]], [[LOAD1]] 90 ; P5600: G_STORE [[MUL]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c) 91 ; P5600: RetRA 92 %0:_(p0) = COPY $a0 93 %1:_(p0) = COPY $a1 94 %2:_(p0) = COPY $a2 95 %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a) 96 %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b) 97 %5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.mulv.w), %3(<4 x s32>), %4(<4 x s32>) 98 G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c) 99 RetRA 100 101... 102--- 103name: mul_v2i64_builtin 104alignment: 4 105tracksRegLiveness: true 106body: | 107 bb.1.entry: 108 liveins: $a0, $a1, $a2 109 110 ; P5600-LABEL: name: mul_v2i64_builtin 111 ; P5600: liveins: $a0, $a1, $a2 112 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 113 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1 114 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2 115 ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a) 116 ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b) 117 ; P5600: [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[LOAD]], [[LOAD1]] 118 ; P5600: G_STORE [[MUL]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c) 119 ; P5600: RetRA 120 %0:_(p0) = COPY $a0 121 %1:_(p0) = COPY $a1 122 %2:_(p0) = COPY $a2 123 %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a) 124 %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b) 125 %5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.mulv.d), %3(<2 x s64>), %4(<2 x s64>) 126 G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c) 127 RetRA 128 129... 130