xref: /llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir (revision 3a106e5b2cd9f4073b2961b991ebaeee96786309) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
3--- |
4
5  define void @mul_i32() {entry: ret void}
6  define void @mul_i8_sext() {entry: ret void}
7  define void @mul_i8_zext() {entry: ret void}
8  define void @mul_i8_aext() {entry: ret void}
9  define void @mul_i16_sext() {entry: ret void}
10  define void @mul_i16_zext() {entry: ret void}
11  define void @mul_i16_aext() {entry: ret void}
12  define void @mul_i64() {entry: ret void}
13  define void @mul_i128() {entry: ret void}
14  define void @umulh_i64() {entry: ret void}
15  define void @umul_with_overflow(i32 %lhs, i32 %rhs, ptr %pmul, ptr %pcarry_flag) { ret void }
16
17...
18---
19name:            mul_i32
20alignment:       4
21tracksRegLiveness: true
22body:             |
23  bb.0.entry:
24    liveins: $a0, $a1
25
26    ; MIPS32-LABEL: name: mul_i32
27    ; MIPS32: liveins: $a0, $a1
28    ; MIPS32-NEXT: {{  $}}
29    ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
30    ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
31    ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
32    ; MIPS32-NEXT: $v0 = COPY [[MUL]](s32)
33    ; MIPS32-NEXT: RetRA implicit $v0
34    %0:_(s32) = COPY $a0
35    %1:_(s32) = COPY $a1
36    %2:_(s32) = G_MUL %0, %1
37    $v0 = COPY %2(s32)
38    RetRA implicit $v0
39
40...
41---
42name:            mul_i8_sext
43alignment:       4
44tracksRegLiveness: true
45body:             |
46  bb.1.entry:
47    liveins: $a0, $a1
48
49    ; MIPS32-LABEL: name: mul_i8_sext
50    ; MIPS32: liveins: $a0, $a1
51    ; MIPS32-NEXT: {{  $}}
52    ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
53    ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
54    ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
55    ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
56    ; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[MUL]], [[C]](s32)
57    ; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
58    ; MIPS32-NEXT: $v0 = COPY [[ASHR]](s32)
59    ; MIPS32-NEXT: RetRA implicit $v0
60    %2:_(s32) = COPY $a0
61    %0:_(s8) = G_TRUNC %2(s32)
62    %3:_(s32) = COPY $a1
63    %1:_(s8) = G_TRUNC %3(s32)
64    %4:_(s8) = G_MUL %1, %0
65    %5:_(s32) = G_SEXT %4(s8)
66    $v0 = COPY %5(s32)
67    RetRA implicit $v0
68
69...
70---
71name:            mul_i8_zext
72alignment:       4
73tracksRegLiveness: true
74body:             |
75  bb.1.entry:
76    liveins: $a0, $a1
77
78    ; MIPS32-LABEL: name: mul_i8_zext
79    ; MIPS32: liveins: $a0, $a1
80    ; MIPS32-NEXT: {{  $}}
81    ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
82    ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
83    ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
84    ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
85    ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
86    ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
87    ; MIPS32-NEXT: RetRA implicit $v0
88    %2:_(s32) = COPY $a0
89    %0:_(s8) = G_TRUNC %2(s32)
90    %3:_(s32) = COPY $a1
91    %1:_(s8) = G_TRUNC %3(s32)
92    %4:_(s8) = G_MUL %1, %0
93    %5:_(s32) = G_ZEXT %4(s8)
94    $v0 = COPY %5(s32)
95    RetRA implicit $v0
96
97...
98---
99name:            mul_i8_aext
100alignment:       4
101tracksRegLiveness: true
102body:             |
103  bb.1.entry:
104    liveins: $a0, $a1
105
106    ; MIPS32-LABEL: name: mul_i8_aext
107    ; MIPS32: liveins: $a0, $a1
108    ; MIPS32-NEXT: {{  $}}
109    ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
110    ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
111    ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
112    ; MIPS32-NEXT: $v0 = COPY [[MUL]](s32)
113    ; MIPS32-NEXT: RetRA implicit $v0
114    %2:_(s32) = COPY $a0
115    %0:_(s8) = G_TRUNC %2(s32)
116    %3:_(s32) = COPY $a1
117    %1:_(s8) = G_TRUNC %3(s32)
118    %4:_(s8) = G_MUL %1, %0
119    %5:_(s32) = G_ANYEXT %4(s8)
120    $v0 = COPY %5(s32)
121    RetRA implicit $v0
122
123...
124---
125name:            mul_i16_sext
126alignment:       4
127tracksRegLiveness: true
128body:             |
129  bb.1.entry:
130    liveins: $a0, $a1
131
132    ; MIPS32-LABEL: name: mul_i16_sext
133    ; MIPS32: liveins: $a0, $a1
134    ; MIPS32-NEXT: {{  $}}
135    ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
136    ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
137    ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
138    ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
139    ; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[MUL]], [[C]](s32)
140    ; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
141    ; MIPS32-NEXT: $v0 = COPY [[ASHR]](s32)
142    ; MIPS32-NEXT: RetRA implicit $v0
143    %2:_(s32) = COPY $a0
144    %0:_(s16) = G_TRUNC %2(s32)
145    %3:_(s32) = COPY $a1
146    %1:_(s16) = G_TRUNC %3(s32)
147    %4:_(s16) = G_MUL %1, %0
148    %5:_(s32) = G_SEXT %4(s16)
149    $v0 = COPY %5(s32)
150    RetRA implicit $v0
151
152...
153---
154name:            mul_i16_zext
155alignment:       4
156tracksRegLiveness: true
157body:             |
158  bb.1.entry:
159    liveins: $a0, $a1
160
161    ; MIPS32-LABEL: name: mul_i16_zext
162    ; MIPS32: liveins: $a0, $a1
163    ; MIPS32-NEXT: {{  $}}
164    ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
165    ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
166    ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
167    ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
168    ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
169    ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
170    ; MIPS32-NEXT: RetRA implicit $v0
171    %2:_(s32) = COPY $a0
172    %0:_(s16) = G_TRUNC %2(s32)
173    %3:_(s32) = COPY $a1
174    %1:_(s16) = G_TRUNC %3(s32)
175    %4:_(s16) = G_MUL %1, %0
176    %5:_(s32) = G_ZEXT %4(s16)
177    $v0 = COPY %5(s32)
178    RetRA implicit $v0
179
180...
181---
182name:            mul_i16_aext
183alignment:       4
184tracksRegLiveness: true
185body:             |
186  bb.1.entry:
187    liveins: $a0, $a1
188
189    ; MIPS32-LABEL: name: mul_i16_aext
190    ; MIPS32: liveins: $a0, $a1
191    ; MIPS32-NEXT: {{  $}}
192    ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
193    ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
194    ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
195    ; MIPS32-NEXT: $v0 = COPY [[MUL]](s32)
196    ; MIPS32-NEXT: RetRA implicit $v0
197    %2:_(s32) = COPY $a0
198    %0:_(s16) = G_TRUNC %2(s32)
199    %3:_(s32) = COPY $a1
200    %1:_(s16) = G_TRUNC %3(s32)
201    %4:_(s16) = G_MUL %1, %0
202    %5:_(s32) = G_ANYEXT %4(s16)
203    $v0 = COPY %5(s32)
204    RetRA implicit $v0
205
206...
207---
208name:            mul_i64
209alignment:       4
210tracksRegLiveness: true
211body:             |
212  bb.1.entry:
213    liveins: $a0, $a1, $a2, $a3
214
215    ; MIPS32-LABEL: name: mul_i64
216    ; MIPS32: liveins: $a0, $a1, $a2, $a3
217    ; MIPS32-NEXT: {{  $}}
218    ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
219    ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
220    ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
221    ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
222    ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY]]
223    ; MIPS32-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY]]
224    ; MIPS32-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY1]]
225    ; MIPS32-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY]]
226    ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
227    ; MIPS32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
228    ; MIPS32-NEXT: $v0 = COPY [[MUL]](s32)
229    ; MIPS32-NEXT: $v1 = COPY [[ADD1]](s32)
230    ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
231    %2:_(s32) = COPY $a0
232    %3:_(s32) = COPY $a1
233    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
234    %4:_(s32) = COPY $a2
235    %5:_(s32) = COPY $a3
236    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
237    %6:_(s64) = G_MUL %1, %0
238    %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
239    $v0 = COPY %7(s32)
240    $v1 = COPY %8(s32)
241    RetRA implicit $v0, implicit $v1
242
243...
244---
245name:            mul_i128
246alignment:       4
247tracksRegLiveness: true
248fixedStack:
249  - { id: 0, offset: 28, size: 4, alignment: 4, stack-id: default, isImmutable: true }
250  - { id: 1, offset: 24, size: 4, alignment: 8, stack-id: default, isImmutable: true }
251  - { id: 2, offset: 20, size: 4, alignment: 4, stack-id: default, isImmutable: true }
252  - { id: 3, offset: 16, size: 4, alignment: 8, stack-id: default, isImmutable: true }
253body:             |
254  bb.1.entry:
255    liveins: $a0, $a1, $a2, $a3
256
257    ; MIPS32-LABEL: name: mul_i128
258    ; MIPS32: liveins: $a0, $a1, $a2, $a3
259    ; MIPS32-NEXT: {{  $}}
260    ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
261    ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
262    ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
263    ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
264    ; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
265    ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
266    ; MIPS32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
267    ; MIPS32-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.1)
268    ; MIPS32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
269    ; MIPS32-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (s32) from %fixed-stack.2, align 8)
270    ; MIPS32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
271    ; MIPS32-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load (s32) from %fixed-stack.3)
272    ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY]]
273    ; MIPS32-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[LOAD1]], [[COPY]]
274    ; MIPS32-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY1]]
275    ; MIPS32-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY]]
276    ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
277    ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL2]]
278    ; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
279    ; MIPS32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[UMULH]]
280    ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]]
281    ; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
282    ; MIPS32-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ICMP]], [[ICMP1]]
283    ; MIPS32-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[LOAD2]], [[COPY]]
284    ; MIPS32-NEXT: [[MUL4:%[0-9]+]]:_(s32) = G_MUL [[LOAD1]], [[COPY1]]
285    ; MIPS32-NEXT: [[MUL5:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY2]]
286    ; MIPS32-NEXT: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[LOAD1]], [[COPY]]
287    ; MIPS32-NEXT: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY1]]
288    ; MIPS32-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL3]], [[MUL4]]
289    ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[MUL4]]
290    ; MIPS32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD3]](s32)
291    ; MIPS32-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[COPY6]], [[MUL5]]
292    ; MIPS32-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[MUL5]]
293    ; MIPS32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD4]](s32)
294    ; MIPS32-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ICMP2]], [[ICMP3]]
295    ; MIPS32-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[COPY7]], [[UMULH1]]
296    ; MIPS32-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD6]](s32), [[UMULH1]]
297    ; MIPS32-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ADD6]](s32)
298    ; MIPS32-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[ICMP4]]
299    ; MIPS32-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[COPY8]], [[UMULH2]]
300    ; MIPS32-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD8]](s32), [[UMULH2]]
301    ; MIPS32-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[ADD8]](s32)
302    ; MIPS32-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[ICMP5]]
303    ; MIPS32-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[COPY9]], [[ADD2]]
304    ; MIPS32-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD10]](s32), [[ADD2]]
305    ; MIPS32-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ADD10]](s32)
306    ; MIPS32-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ICMP6]]
307    ; MIPS32-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[LOAD3]], [[COPY]]
308    ; MIPS32-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[LOAD2]], [[COPY1]]
309    ; MIPS32-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[LOAD1]], [[COPY2]]
310    ; MIPS32-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY3]]
311    ; MIPS32-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[LOAD2]], [[COPY]]
312    ; MIPS32-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[LOAD1]], [[COPY1]]
313    ; MIPS32-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY2]]
314    ; MIPS32-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[MUL6]], [[MUL7]]
315    ; MIPS32-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ADD12]], [[MUL8]]
316    ; MIPS32-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[MUL9]]
317    ; MIPS32-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[UMULH3]]
318    ; MIPS32-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[ADD15]], [[UMULH4]]
319    ; MIPS32-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH5]]
320    ; MIPS32-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[ADD11]]
321    ; MIPS32-NEXT: $v0 = COPY [[MUL]](s32)
322    ; MIPS32-NEXT: $v1 = COPY [[COPY5]](s32)
323    ; MIPS32-NEXT: $a0 = COPY [[COPY10]](s32)
324    ; MIPS32-NEXT: $a1 = COPY [[ADD18]](s32)
325    ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
326    %2:_(s32) = COPY $a0
327    %3:_(s32) = COPY $a1
328    %4:_(s32) = COPY $a2
329    %5:_(s32) = COPY $a3
330    %0:_(s128) = G_MERGE_VALUES %2(s32), %3(s32), %4(s32), %5(s32)
331    %10:_(p0) = G_FRAME_INDEX %fixed-stack.3
332    %6:_(s32) = G_LOAD %10(p0) :: (load (s32) from %fixed-stack.3, align 8)
333    %11:_(p0) = G_FRAME_INDEX %fixed-stack.2
334    %7:_(s32) = G_LOAD %11(p0) :: (load (s32) from %fixed-stack.2)
335    %12:_(p0) = G_FRAME_INDEX %fixed-stack.1
336    %8:_(s32) = G_LOAD %12(p0) :: (load (s32) from %fixed-stack.1, align 8)
337    %13:_(p0) = G_FRAME_INDEX %fixed-stack.0
338    %9:_(s32) = G_LOAD %13(p0) :: (load (s32) from %fixed-stack.0)
339    %1:_(s128) = G_MERGE_VALUES %6(s32), %7(s32), %8(s32), %9(s32)
340    %14:_(s128) = G_MUL %1, %0
341    %15:_(s32), %16:_(s32), %17:_(s32), %18:_(s32) = G_UNMERGE_VALUES %14(s128)
342    $v0 = COPY %15(s32)
343    $v1 = COPY %16(s32)
344    $a0 = COPY %17(s32)
345    $a1 = COPY %18(s32)
346    RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
347
348...
349---
350name:            umulh_i64
351alignment:       4
352tracksRegLiveness: true
353body:             |
354  bb.1.entry:
355    liveins: $a0, $a1, $a2, $a3
356
357    ; MIPS32-LABEL: name: umulh_i64
358    ; MIPS32: liveins: $a0, $a1, $a2, $a3
359    ; MIPS32-NEXT: {{  $}}
360    ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
361    ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
362    ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
363    ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
364    ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY]]
365    ; MIPS32-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY1]]
366    ; MIPS32-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY]]
367    ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL]], [[MUL1]]
368    ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL1]]
369    ; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
370    ; MIPS32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[UMULH]]
371    ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]]
372    ; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
373    ; MIPS32-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ICMP]], [[ICMP1]]
374    ; MIPS32-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY1]]
375    ; MIPS32-NEXT: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[COPY3]], [[COPY]]
376    ; MIPS32-NEXT: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY1]]
377    ; MIPS32-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL2]], [[UMULH1]]
378    ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[UMULH1]]
379    ; MIPS32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD3]](s32)
380    ; MIPS32-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[COPY6]], [[UMULH2]]
381    ; MIPS32-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[UMULH2]]
382    ; MIPS32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD4]](s32)
383    ; MIPS32-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ICMP2]], [[ICMP3]]
384    ; MIPS32-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[COPY7]], [[ADD2]]
385    ; MIPS32-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD6]](s32), [[ADD2]]
386    ; MIPS32-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ADD6]](s32)
387    ; MIPS32-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[ICMP4]]
388    ; MIPS32-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[COPY3]], [[COPY1]]
389    ; MIPS32-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[UMULH3]], [[ADD7]]
390    ; MIPS32-NEXT: $v0 = COPY [[COPY8]](s32)
391    ; MIPS32-NEXT: $v1 = COPY [[ADD8]](s32)
392    ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
393    %2:_(s32) = COPY $a0
394    %3:_(s32) = COPY $a1
395    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
396    %4:_(s32) = COPY $a2
397    %5:_(s32) = COPY $a3
398    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
399    %6:_(s64) = G_UMULH %1, %0
400    %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
401    $v0 = COPY %7(s32)
402    $v1 = COPY %8(s32)
403    RetRA implicit $v0, implicit $v1
404
405...
406---
407name:            umul_with_overflow
408alignment:       4
409tracksRegLiveness: true
410body:             |
411  bb.1 (%ir-block.0):
412    liveins: $a0, $a1, $a2, $a3
413
414    ; MIPS32-LABEL: name: umul_with_overflow
415    ; MIPS32: liveins: $a0, $a1, $a2, $a3
416    ; MIPS32-NEXT: {{  $}}
417    ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
418    ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
419    ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
420    ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $a3
421    ; MIPS32-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[COPY1]]
422    ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
423    ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
424    ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]]
425    ; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
426    ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
427    ; MIPS32-NEXT: G_STORE [[AND]](s32), [[COPY3]](p0) :: (store (s8) into %ir.pcarry_flag)
428    ; MIPS32-NEXT: G_STORE [[MUL]](s32), [[COPY2]](p0) :: (store (s32) into %ir.pmul)
429    ; MIPS32-NEXT: RetRA
430    %0:_(s32) = COPY $a0
431    %1:_(s32) = COPY $a1
432    %2:_(p0) = COPY $a2
433    %3:_(p0) = COPY $a3
434    %4:_(s32), %5:_(s1) = G_UMULO %0, %1
435    G_STORE %5(s1), %3(p0) :: (store (s1) into %ir.pcarry_flag)
436    G_STORE %4(s32), %2(p0) :: (store (s32) into %ir.pmul)
437    RetRA
438
439...
440