1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
3--- |
4
5  declare <4 x float> @llvm.mips.fadd.w(<4 x float>, <4 x float>)
6  define void @fadd_v4f32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
7
8  declare <2 x double> @llvm.mips.fadd.d(<2 x double>, <2 x double>)
9  define void @fadd_v2f64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
10
11  declare <4 x float> @llvm.mips.fsub.w(<4 x float>, <4 x float>)
12  define void @fsub_v4f32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
13
14  declare <2 x double> @llvm.mips.fsub.d(<2 x double>, <2 x double>)
15  define void @fsub_v2f64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
16
17  declare <4 x float> @llvm.mips.fmul.w(<4 x float>, <4 x float>)
18  define void @fmul_v4f32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
19
20  declare <2 x double> @llvm.mips.fmul.d(<2 x double>, <2 x double>)
21  define void @fmul_v2f64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
22
23  declare <4 x float> @llvm.mips.fdiv.w(<4 x float>, <4 x float>)
24  define void @fdiv_v4f32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
25
26  declare <2 x double> @llvm.mips.fdiv.d(<2 x double>, <2 x double>)
27  define void @fdiv_v2f64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }
28
29...
30---
31name:            fadd_v4f32_builtin
32alignment:       4
33tracksRegLiveness: true
34body:             |
35  bb.1.entry:
36    liveins: $a0, $a1, $a2
37
38    ; P5600-LABEL: name: fadd_v4f32_builtin
39    ; P5600: liveins: $a0, $a1, $a2
40    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
41    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
42    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
43    ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
44    ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
45    ; P5600: [[FADD:%[0-9]+]]:_(<4 x s32>) = G_FADD [[LOAD]], [[LOAD1]]
46    ; P5600: G_STORE [[FADD]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
47    ; P5600: RetRA
48    %0:_(p0) = COPY $a0
49    %1:_(p0) = COPY $a1
50    %2:_(p0) = COPY $a2
51    %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
52    %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
53    %5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.fadd.w), %3(<4 x s32>), %4(<4 x s32>)
54    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
55    RetRA
56
57...
58---
59name:            fadd_v2f64_builtin
60alignment:       4
61tracksRegLiveness: true
62body:             |
63  bb.1.entry:
64    liveins: $a0, $a1, $a2
65
66    ; P5600-LABEL: name: fadd_v2f64_builtin
67    ; P5600: liveins: $a0, $a1, $a2
68    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
69    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
70    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
71    ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
72    ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
73    ; P5600: [[FADD:%[0-9]+]]:_(<2 x s64>) = G_FADD [[LOAD]], [[LOAD1]]
74    ; P5600: G_STORE [[FADD]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
75    ; P5600: RetRA
76    %0:_(p0) = COPY $a0
77    %1:_(p0) = COPY $a1
78    %2:_(p0) = COPY $a2
79    %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
80    %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
81    %5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.fadd.d), %3(<2 x s64>), %4(<2 x s64>)
82    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
83    RetRA
84
85...
86---
87name:            fsub_v4f32_builtin
88alignment:       4
89tracksRegLiveness: true
90body:             |
91  bb.1.entry:
92    liveins: $a0, $a1, $a2
93
94    ; P5600-LABEL: name: fsub_v4f32_builtin
95    ; P5600: liveins: $a0, $a1, $a2
96    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
97    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
98    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
99    ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
100    ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
101    ; P5600: [[FSUB:%[0-9]+]]:_(<4 x s32>) = G_FSUB [[LOAD]], [[LOAD1]]
102    ; P5600: G_STORE [[FSUB]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
103    ; P5600: RetRA
104    %0:_(p0) = COPY $a0
105    %1:_(p0) = COPY $a1
106    %2:_(p0) = COPY $a2
107    %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
108    %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
109    %5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.fsub.w), %3(<4 x s32>), %4(<4 x s32>)
110    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
111    RetRA
112
113...
114---
115name:            fsub_v2f64_builtin
116alignment:       4
117tracksRegLiveness: true
118body:             |
119  bb.1.entry:
120    liveins: $a0, $a1, $a2
121
122    ; P5600-LABEL: name: fsub_v2f64_builtin
123    ; P5600: liveins: $a0, $a1, $a2
124    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
125    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
126    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
127    ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
128    ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
129    ; P5600: [[FSUB:%[0-9]+]]:_(<2 x s64>) = G_FSUB [[LOAD]], [[LOAD1]]
130    ; P5600: G_STORE [[FSUB]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
131    ; P5600: RetRA
132    %0:_(p0) = COPY $a0
133    %1:_(p0) = COPY $a1
134    %2:_(p0) = COPY $a2
135    %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
136    %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
137    %5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.fsub.d), %3(<2 x s64>), %4(<2 x s64>)
138    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
139    RetRA
140
141...
142---
143name:            fmul_v4f32_builtin
144alignment:       4
145tracksRegLiveness: true
146body:             |
147  bb.1.entry:
148    liveins: $a0, $a1, $a2
149
150    ; P5600-LABEL: name: fmul_v4f32_builtin
151    ; P5600: liveins: $a0, $a1, $a2
152    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
153    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
154    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
155    ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
156    ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
157    ; P5600: [[FMUL:%[0-9]+]]:_(<4 x s32>) = G_FMUL [[LOAD]], [[LOAD1]]
158    ; P5600: G_STORE [[FMUL]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
159    ; P5600: RetRA
160    %0:_(p0) = COPY $a0
161    %1:_(p0) = COPY $a1
162    %2:_(p0) = COPY $a2
163    %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
164    %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
165    %5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.fmul.w), %3(<4 x s32>), %4(<4 x s32>)
166    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
167    RetRA
168
169...
170---
171name:            fmul_v2f64_builtin
172alignment:       4
173tracksRegLiveness: true
174body:             |
175  bb.1.entry:
176    liveins: $a0, $a1, $a2
177
178    ; P5600-LABEL: name: fmul_v2f64_builtin
179    ; P5600: liveins: $a0, $a1, $a2
180    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
181    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
182    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
183    ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
184    ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
185    ; P5600: [[FMUL:%[0-9]+]]:_(<2 x s64>) = G_FMUL [[LOAD]], [[LOAD1]]
186    ; P5600: G_STORE [[FMUL]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
187    ; P5600: RetRA
188    %0:_(p0) = COPY $a0
189    %1:_(p0) = COPY $a1
190    %2:_(p0) = COPY $a2
191    %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
192    %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
193    %5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.fmul.d), %3(<2 x s64>), %4(<2 x s64>)
194    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
195    RetRA
196
197...
198---
199name:            fdiv_v4f32_builtin
200alignment:       4
201tracksRegLiveness: true
202body:             |
203  bb.1.entry:
204    liveins: $a0, $a1, $a2
205
206    ; P5600-LABEL: name: fdiv_v4f32_builtin
207    ; P5600: liveins: $a0, $a1, $a2
208    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
209    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
210    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
211    ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
212    ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
213    ; P5600: [[FDIV:%[0-9]+]]:_(<4 x s32>) = G_FDIV [[LOAD]], [[LOAD1]]
214    ; P5600: G_STORE [[FDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
215    ; P5600: RetRA
216    %0:_(p0) = COPY $a0
217    %1:_(p0) = COPY $a1
218    %2:_(p0) = COPY $a2
219    %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
220    %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
221    %5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.fdiv.w), %3(<4 x s32>), %4(<4 x s32>)
222    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
223    RetRA
224
225...
226---
227name:            fdiv_v2f64_builtin
228alignment:       4
229tracksRegLiveness: true
230body:             |
231  bb.1.entry:
232    liveins: $a0, $a1, $a2
233
234    ; P5600-LABEL: name: fdiv_v2f64_builtin
235    ; P5600: liveins: $a0, $a1, $a2
236    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
237    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
238    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
239    ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
240    ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
241    ; P5600: [[FDIV:%[0-9]+]]:_(<2 x s64>) = G_FDIV [[LOAD]], [[LOAD1]]
242    ; P5600: G_STORE [[FDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
243    ; P5600: RetRA
244    %0:_(p0) = COPY $a0
245    %1:_(p0) = COPY $a1
246    %2:_(p0) = COPY $a2
247    %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
248    %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
249    %5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.fdiv.d), %3(<2 x s64>), %4(<2 x s64>)
250    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
251    RetRA
252
253...
254