1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
3--- |
4
5  define void @fadd_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
6  define void @fadd_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }
7
8  define void @fsub_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
9  define void @fsub_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }
10
11  define void @fmul_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
12  define void @fmul_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }
13
14  define void @fdiv_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
15  define void @fdiv_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }
16
17...
18---
19name:            fadd_v4f32
20alignment:       4
21tracksRegLiveness: true
22body:             |
23  bb.1.entry:
24    liveins: $a0, $a1, $a2
25
26    ; P5600-LABEL: name: fadd_v4f32
27    ; P5600: liveins: $a0, $a1, $a2
28    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
29    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
30    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
31    ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
32    ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
33    ; P5600: [[FADD:%[0-9]+]]:_(<4 x s32>) = G_FADD [[LOAD]], [[LOAD1]]
34    ; P5600: G_STORE [[FADD]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
35    ; P5600: RetRA
36    %0:_(p0) = COPY $a0
37    %1:_(p0) = COPY $a1
38    %2:_(p0) = COPY $a2
39    %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
40    %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
41    %5:_(<4 x s32>) = G_FADD %3, %4
42    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
43    RetRA
44
45...
46---
47name:            fadd_v2f64
48alignment:       4
49tracksRegLiveness: true
50body:             |
51  bb.1.entry:
52    liveins: $a0, $a1, $a2
53
54    ; P5600-LABEL: name: fadd_v2f64
55    ; P5600: liveins: $a0, $a1, $a2
56    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
57    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
58    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
59    ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
60    ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
61    ; P5600: [[FADD:%[0-9]+]]:_(<2 x s64>) = G_FADD [[LOAD]], [[LOAD1]]
62    ; P5600: G_STORE [[FADD]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
63    ; P5600: RetRA
64    %0:_(p0) = COPY $a0
65    %1:_(p0) = COPY $a1
66    %2:_(p0) = COPY $a2
67    %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
68    %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
69    %5:_(<2 x s64>) = G_FADD %3, %4
70    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
71    RetRA
72
73...
74---
75name:            fsub_v4f32
76alignment:       4
77tracksRegLiveness: true
78body:             |
79  bb.1.entry:
80    liveins: $a0, $a1, $a2
81
82    ; P5600-LABEL: name: fsub_v4f32
83    ; P5600: liveins: $a0, $a1, $a2
84    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
85    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
86    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
87    ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
88    ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
89    ; P5600: [[FSUB:%[0-9]+]]:_(<4 x s32>) = G_FSUB [[LOAD]], [[LOAD1]]
90    ; P5600: G_STORE [[FSUB]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
91    ; P5600: RetRA
92    %0:_(p0) = COPY $a0
93    %1:_(p0) = COPY $a1
94    %2:_(p0) = COPY $a2
95    %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
96    %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
97    %5:_(<4 x s32>) = G_FSUB %3, %4
98    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
99    RetRA
100
101...
102---
103name:            fsub_v2f64
104alignment:       4
105tracksRegLiveness: true
106body:             |
107  bb.1.entry:
108    liveins: $a0, $a1, $a2
109
110    ; P5600-LABEL: name: fsub_v2f64
111    ; P5600: liveins: $a0, $a1, $a2
112    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
113    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
114    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
115    ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
116    ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
117    ; P5600: [[FSUB:%[0-9]+]]:_(<2 x s64>) = G_FSUB [[LOAD]], [[LOAD1]]
118    ; P5600: G_STORE [[FSUB]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
119    ; P5600: RetRA
120    %0:_(p0) = COPY $a0
121    %1:_(p0) = COPY $a1
122    %2:_(p0) = COPY $a2
123    %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
124    %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
125    %5:_(<2 x s64>) = G_FSUB %3, %4
126    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
127    RetRA
128
129...
130---
131name:            fmul_v4f32
132alignment:       4
133tracksRegLiveness: true
134body:             |
135  bb.1.entry:
136    liveins: $a0, $a1, $a2
137
138    ; P5600-LABEL: name: fmul_v4f32
139    ; P5600: liveins: $a0, $a1, $a2
140    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
141    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
142    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
143    ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
144    ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
145    ; P5600: [[FMUL:%[0-9]+]]:_(<4 x s32>) = G_FMUL [[LOAD]], [[LOAD1]]
146    ; P5600: G_STORE [[FMUL]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
147    ; P5600: RetRA
148    %0:_(p0) = COPY $a0
149    %1:_(p0) = COPY $a1
150    %2:_(p0) = COPY $a2
151    %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
152    %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
153    %5:_(<4 x s32>) = G_FMUL %3, %4
154    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
155    RetRA
156
157...
158---
159name:            fmul_v2f64
160alignment:       4
161tracksRegLiveness: true
162body:             |
163  bb.1.entry:
164    liveins: $a0, $a1, $a2
165
166    ; P5600-LABEL: name: fmul_v2f64
167    ; P5600: liveins: $a0, $a1, $a2
168    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
169    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
170    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
171    ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
172    ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
173    ; P5600: [[FMUL:%[0-9]+]]:_(<2 x s64>) = G_FMUL [[LOAD]], [[LOAD1]]
174    ; P5600: G_STORE [[FMUL]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
175    ; P5600: RetRA
176    %0:_(p0) = COPY $a0
177    %1:_(p0) = COPY $a1
178    %2:_(p0) = COPY $a2
179    %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
180    %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
181    %5:_(<2 x s64>) = G_FMUL %3, %4
182    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
183    RetRA
184
185...
186---
187name:            fdiv_v4f32
188alignment:       4
189tracksRegLiveness: true
190body:             |
191  bb.1.entry:
192    liveins: $a0, $a1, $a2
193
194    ; P5600-LABEL: name: fdiv_v4f32
195    ; P5600: liveins: $a0, $a1, $a2
196    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
197    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
198    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
199    ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
200    ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
201    ; P5600: [[FDIV:%[0-9]+]]:_(<4 x s32>) = G_FDIV [[LOAD]], [[LOAD1]]
202    ; P5600: G_STORE [[FDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
203    ; P5600: RetRA
204    %0:_(p0) = COPY $a0
205    %1:_(p0) = COPY $a1
206    %2:_(p0) = COPY $a2
207    %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
208    %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
209    %5:_(<4 x s32>) = G_FDIV %3, %4
210    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
211    RetRA
212
213...
214---
215name:            fdiv_v2f64
216alignment:       4
217tracksRegLiveness: true
218body:             |
219  bb.1.entry:
220    liveins: $a0, $a1, $a2
221
222    ; P5600-LABEL: name: fdiv_v2f64
223    ; P5600: liveins: $a0, $a1, $a2
224    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
225    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
226    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
227    ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
228    ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
229    ; P5600: [[FDIV:%[0-9]+]]:_(<2 x s64>) = G_FDIV [[LOAD]], [[LOAD1]]
230    ; P5600: G_STORE [[FDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
231    ; P5600: RetRA
232    %0:_(p0) = COPY $a0
233    %1:_(p0) = COPY $a1
234    %2:_(p0) = COPY $a2
235    %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
236    %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
237    %5:_(<2 x s64>) = G_FDIV %3, %4
238    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
239    RetRA
240
241...
242