xref: /llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sitofp_and_uitofp.mir (revision 92c80529ddb3ae147e9e58aed8d68b4aa2ea2379) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
3# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
4--- |
5
6  define void @i32tof32() {entry: ret void}
7  define void @i32tof64() {entry: ret void}
8  define void @u32tof64() {entry: ret void}
9
10...
11---
12name:            i32tof32
13alignment:       4
14legalized:       true
15regBankSelected: true
16tracksRegLiveness: true
17body:             |
18  bb.1.entry:
19    liveins: $a0
20
21    ; FP32-LABEL: name: i32tof32
22    ; FP32: liveins: $a0
23    ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
24    ; FP32: [[PseudoCVT_S_W:%[0-9]+]]:fgr32 = PseudoCVT_S_W [[COPY]]
25    ; FP32: $f0 = COPY [[PseudoCVT_S_W]]
26    ; FP32: RetRA implicit $f0
27    ; FP64-LABEL: name: i32tof32
28    ; FP64: liveins: $a0
29    ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
30    ; FP64: [[PseudoCVT_S_W:%[0-9]+]]:fgr32 = PseudoCVT_S_W [[COPY]]
31    ; FP64: $f0 = COPY [[PseudoCVT_S_W]]
32    ; FP64: RetRA implicit $f0
33    %0:gprb(s32) = COPY $a0
34    %1:fprb(s32) = G_SITOFP %0(s32)
35    $f0 = COPY %1(s32)
36    RetRA implicit $f0
37
38...
39---
40name:            i32tof64
41alignment:       4
42legalized:       true
43regBankSelected: true
44tracksRegLiveness: true
45body:             |
46  bb.1.entry:
47    liveins: $a0
48
49    ; FP32-LABEL: name: i32tof64
50    ; FP32: liveins: $a0
51    ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
52    ; FP32: [[PseudoCVT_D32_W:%[0-9]+]]:afgr64 = PseudoCVT_D32_W [[COPY]]
53    ; FP32: $d0 = COPY [[PseudoCVT_D32_W]]
54    ; FP32: RetRA implicit $d0
55    ; FP64-LABEL: name: i32tof64
56    ; FP64: liveins: $a0
57    ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
58    ; FP64: [[PseudoCVT_D64_W:%[0-9]+]]:fgr64 = PseudoCVT_D64_W [[COPY]]
59    ; FP64: $d0 = COPY [[PseudoCVT_D64_W]]
60    ; FP64: RetRA implicit $d0
61    %0:gprb(s32) = COPY $a0
62    %1:fprb(s64) = G_SITOFP %0(s32)
63    $d0 = COPY %1(s64)
64    RetRA implicit $d0
65
66...
67---
68name:            u32tof64
69alignment:       4
70legalized:       true
71regBankSelected: true
72tracksRegLiveness: true
73body:             |
74  bb.1.entry:
75    liveins: $a0
76
77    ; FP32-LABEL: name: u32tof64
78    ; FP32: liveins: $a0
79    ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
80    ; FP32: [[LUi:%[0-9]+]]:gpr32 = LUi 17200
81    ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64 = BuildPairF64 [[COPY]], [[LUi]]
82    ; FP32: [[LUi1:%[0-9]+]]:gpr32 = LUi 17200
83    ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
84    ; FP32: [[BuildPairF64_1:%[0-9]+]]:afgr64 = BuildPairF64 [[ORi]], [[LUi1]]
85    ; FP32: [[FSUB_D32_:%[0-9]+]]:afgr64 = FSUB_D32 [[BuildPairF64_]], [[BuildPairF64_1]]
86    ; FP32: $d0 = COPY [[FSUB_D32_]]
87    ; FP32: RetRA implicit $d0
88    ; FP64-LABEL: name: u32tof64
89    ; FP64: liveins: $a0
90    ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
91    ; FP64: [[LUi:%[0-9]+]]:gpr32 = LUi 17200
92    ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64 = BuildPairF64_64 [[COPY]], [[LUi]]
93    ; FP64: [[LUi1:%[0-9]+]]:gpr32 = LUi 17200
94    ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
95    ; FP64: [[BuildPairF64_64_1:%[0-9]+]]:fgr64 = BuildPairF64_64 [[ORi]], [[LUi1]]
96    ; FP64: [[FSUB_D64_:%[0-9]+]]:fgr64 = FSUB_D64 [[BuildPairF64_64_]], [[BuildPairF64_64_1]]
97    ; FP64: $d0 = COPY [[FSUB_D64_]]
98    ; FP64: RetRA implicit $d0
99    %0:gprb(s32) = COPY $a0
100    %2:gprb(s32) = G_CONSTANT i32 1127219200
101    %3:fprb(s64) = G_MERGE_VALUES %0(s32), %2(s32)
102    %4:fprb(s64) = G_FCONSTANT double 0x4330000000000000
103    %1:fprb(s64) = G_FSUB %3, %4
104    $d0 = COPY %1(s64)
105    RetRA implicit $d0
106
107...
108