xref: /llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div_vec.mir (revision 60442f0d442723a487528bdd8b48b24657a025e8) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
3--- |
4
5  define void @sdiv_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
6  define void @sdiv_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }
7  define void @sdiv_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }
8  define void @sdiv_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }
9
10  define void @srem_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
11  define void @srem_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }
12  define void @srem_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }
13  define void @srem_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }
14
15  define void @udiv_v16u8(ptr %a, ptr %b, ptr %c) { entry: ret void }
16  define void @udiv_v8u16(ptr %a, ptr %b, ptr %c) { entry: ret void }
17  define void @udiv_v4u32(ptr %a, ptr %b, ptr %c) { entry: ret void }
18  define void @udiv_v2u64(ptr %a, ptr %b, ptr %c) { entry: ret void }
19
20  define void @urem_v16u8(ptr %a, ptr %b, ptr %c) { entry: ret void }
21  define void @urem_v8u16(ptr %a, ptr %b, ptr %c) { entry: ret void }
22  define void @urem_v4u32(ptr %a, ptr %b, ptr %c) { entry: ret void }
23  define void @urem_v2u64(ptr %a, ptr %b, ptr %c) { entry: ret void }
24
25...
26---
27name:            sdiv_v16i8
28alignment:       4
29legalized:       true
30regBankSelected: true
31tracksRegLiveness: true
32body:             |
33  bb.1.entry:
34    liveins: $a0, $a1, $a2
35
36    ; P5600-LABEL: name: sdiv_v16i8
37    ; P5600: liveins: $a0, $a1, $a2
38    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
39    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
40    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
41    ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load (<16 x s8>) from %ir.a)
42    ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load (<16 x s8>) from %ir.b)
43    ; P5600: [[DIV_S_B:%[0-9]+]]:msa128b = DIV_S_B [[LD_B]], [[LD_B1]]
44    ; P5600: ST_B [[DIV_S_B]], [[COPY2]], 0 :: (store (<16 x s8>) into %ir.c)
45    ; P5600: RetRA
46    %0:gprb(p0) = COPY $a0
47    %1:gprb(p0) = COPY $a1
48    %2:gprb(p0) = COPY $a2
49    %3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
50    %4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
51    %5:fprb(<16 x s8>) = G_SDIV %3, %4
52    G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)
53    RetRA
54
55...
56---
57name:            sdiv_v8i16
58alignment:       4
59legalized:       true
60regBankSelected: true
61tracksRegLiveness: true
62body:             |
63  bb.1.entry:
64    liveins: $a0, $a1, $a2
65
66    ; P5600-LABEL: name: sdiv_v8i16
67    ; P5600: liveins: $a0, $a1, $a2
68    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
69    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
70    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
71    ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load (<8 x s16>) from %ir.a)
72    ; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load (<8 x s16>) from %ir.b)
73    ; P5600: [[DIV_S_H:%[0-9]+]]:msa128h = DIV_S_H [[LD_H]], [[LD_H1]]
74    ; P5600: ST_H [[DIV_S_H]], [[COPY2]], 0 :: (store (<8 x s16>) into %ir.c)
75    ; P5600: RetRA
76    %0:gprb(p0) = COPY $a0
77    %1:gprb(p0) = COPY $a1
78    %2:gprb(p0) = COPY $a2
79    %3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
80    %4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
81    %5:fprb(<8 x s16>) = G_SDIV %3, %4
82    G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)
83    RetRA
84
85...
86---
87name:            sdiv_v4i32
88alignment:       4
89legalized:       true
90regBankSelected: true
91tracksRegLiveness: true
92body:             |
93  bb.1.entry:
94    liveins: $a0, $a1, $a2
95
96    ; P5600-LABEL: name: sdiv_v4i32
97    ; P5600: liveins: $a0, $a1, $a2
98    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
99    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
100    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
101    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
102    ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
103    ; P5600: [[DIV_S_W:%[0-9]+]]:msa128w = DIV_S_W [[LD_W]], [[LD_W1]]
104    ; P5600: ST_W [[DIV_S_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
105    ; P5600: RetRA
106    %0:gprb(p0) = COPY $a0
107    %1:gprb(p0) = COPY $a1
108    %2:gprb(p0) = COPY $a2
109    %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
110    %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
111    %5:fprb(<4 x s32>) = G_SDIV %3, %4
112    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
113    RetRA
114
115...
116---
117name:            sdiv_v2i64
118alignment:       4
119legalized:       true
120regBankSelected: true
121tracksRegLiveness: true
122body:             |
123  bb.1.entry:
124    liveins: $a0, $a1, $a2
125
126    ; P5600-LABEL: name: sdiv_v2i64
127    ; P5600: liveins: $a0, $a1, $a2
128    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
129    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
130    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
131    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
132    ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
133    ; P5600: [[DIV_S_D:%[0-9]+]]:msa128d = DIV_S_D [[LD_D]], [[LD_D1]]
134    ; P5600: ST_D [[DIV_S_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
135    ; P5600: RetRA
136    %0:gprb(p0) = COPY $a0
137    %1:gprb(p0) = COPY $a1
138    %2:gprb(p0) = COPY $a2
139    %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
140    %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
141    %5:fprb(<2 x s64>) = G_SDIV %3, %4
142    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
143    RetRA
144
145...
146---
147name:            srem_v16i8
148alignment:       4
149legalized:       true
150regBankSelected: true
151tracksRegLiveness: true
152body:             |
153  bb.1.entry:
154    liveins: $a0, $a1, $a2
155
156    ; P5600-LABEL: name: srem_v16i8
157    ; P5600: liveins: $a0, $a1, $a2
158    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
159    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
160    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
161    ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load (<16 x s8>) from %ir.a)
162    ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load (<16 x s8>) from %ir.b)
163    ; P5600: [[MOD_S_B:%[0-9]+]]:msa128b = MOD_S_B [[LD_B]], [[LD_B1]]
164    ; P5600: ST_B [[MOD_S_B]], [[COPY2]], 0 :: (store (<16 x s8>) into %ir.c)
165    ; P5600: RetRA
166    %0:gprb(p0) = COPY $a0
167    %1:gprb(p0) = COPY $a1
168    %2:gprb(p0) = COPY $a2
169    %3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
170    %4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
171    %5:fprb(<16 x s8>) = G_SREM %3, %4
172    G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)
173    RetRA
174
175...
176---
177name:            srem_v8i16
178alignment:       4
179legalized:       true
180regBankSelected: true
181tracksRegLiveness: true
182body:             |
183  bb.1.entry:
184    liveins: $a0, $a1, $a2
185
186    ; P5600-LABEL: name: srem_v8i16
187    ; P5600: liveins: $a0, $a1, $a2
188    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
189    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
190    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
191    ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load (<8 x s16>) from %ir.a)
192    ; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load (<8 x s16>) from %ir.b)
193    ; P5600: [[MOD_S_H:%[0-9]+]]:msa128h = MOD_S_H [[LD_H]], [[LD_H1]]
194    ; P5600: ST_H [[MOD_S_H]], [[COPY2]], 0 :: (store (<8 x s16>) into %ir.c)
195    ; P5600: RetRA
196    %0:gprb(p0) = COPY $a0
197    %1:gprb(p0) = COPY $a1
198    %2:gprb(p0) = COPY $a2
199    %3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
200    %4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
201    %5:fprb(<8 x s16>) = G_SREM %3, %4
202    G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)
203    RetRA
204
205...
206---
207name:            srem_v4i32
208alignment:       4
209legalized:       true
210regBankSelected: true
211tracksRegLiveness: true
212body:             |
213  bb.1.entry:
214    liveins: $a0, $a1, $a2
215
216    ; P5600-LABEL: name: srem_v4i32
217    ; P5600: liveins: $a0, $a1, $a2
218    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
219    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
220    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
221    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
222    ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
223    ; P5600: [[MOD_S_W:%[0-9]+]]:msa128w = MOD_S_W [[LD_W]], [[LD_W1]]
224    ; P5600: ST_W [[MOD_S_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
225    ; P5600: RetRA
226    %0:gprb(p0) = COPY $a0
227    %1:gprb(p0) = COPY $a1
228    %2:gprb(p0) = COPY $a2
229    %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
230    %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
231    %5:fprb(<4 x s32>) = G_SREM %3, %4
232    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
233    RetRA
234
235...
236---
237name:            srem_v2i64
238alignment:       4
239legalized:       true
240regBankSelected: true
241tracksRegLiveness: true
242body:             |
243  bb.1.entry:
244    liveins: $a0, $a1, $a2
245
246    ; P5600-LABEL: name: srem_v2i64
247    ; P5600: liveins: $a0, $a1, $a2
248    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
249    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
250    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
251    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
252    ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
253    ; P5600: [[MOD_S_D:%[0-9]+]]:msa128d = MOD_S_D [[LD_D]], [[LD_D1]]
254    ; P5600: ST_D [[MOD_S_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
255    ; P5600: RetRA
256    %0:gprb(p0) = COPY $a0
257    %1:gprb(p0) = COPY $a1
258    %2:gprb(p0) = COPY $a2
259    %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
260    %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
261    %5:fprb(<2 x s64>) = G_SREM %3, %4
262    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
263    RetRA
264
265...
266---
267name:            udiv_v16u8
268alignment:       4
269legalized:       true
270regBankSelected: true
271tracksRegLiveness: true
272body:             |
273  bb.1.entry:
274    liveins: $a0, $a1, $a2
275
276    ; P5600-LABEL: name: udiv_v16u8
277    ; P5600: liveins: $a0, $a1, $a2
278    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
279    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
280    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
281    ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load (<16 x s8>) from %ir.a)
282    ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load (<16 x s8>) from %ir.b)
283    ; P5600: [[DIV_U_B:%[0-9]+]]:msa128b = DIV_U_B [[LD_B]], [[LD_B1]]
284    ; P5600: ST_B [[DIV_U_B]], [[COPY2]], 0 :: (store (<16 x s8>) into %ir.c)
285    ; P5600: RetRA
286    %0:gprb(p0) = COPY $a0
287    %1:gprb(p0) = COPY $a1
288    %2:gprb(p0) = COPY $a2
289    %3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
290    %4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
291    %5:fprb(<16 x s8>) = G_UDIV %3, %4
292    G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)
293    RetRA
294
295...
296---
297name:            udiv_v8u16
298alignment:       4
299legalized:       true
300regBankSelected: true
301tracksRegLiveness: true
302body:             |
303  bb.1.entry:
304    liveins: $a0, $a1, $a2
305
306    ; P5600-LABEL: name: udiv_v8u16
307    ; P5600: liveins: $a0, $a1, $a2
308    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
309    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
310    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
311    ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load (<8 x s16>) from %ir.a)
312    ; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load (<8 x s16>) from %ir.b)
313    ; P5600: [[DIV_U_H:%[0-9]+]]:msa128h = DIV_U_H [[LD_H]], [[LD_H1]]
314    ; P5600: ST_H [[DIV_U_H]], [[COPY2]], 0 :: (store (<8 x s16>) into %ir.c)
315    ; P5600: RetRA
316    %0:gprb(p0) = COPY $a0
317    %1:gprb(p0) = COPY $a1
318    %2:gprb(p0) = COPY $a2
319    %3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
320    %4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
321    %5:fprb(<8 x s16>) = G_UDIV %3, %4
322    G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)
323    RetRA
324
325...
326---
327name:            udiv_v4u32
328alignment:       4
329legalized:       true
330regBankSelected: true
331tracksRegLiveness: true
332body:             |
333  bb.1.entry:
334    liveins: $a0, $a1, $a2
335
336    ; P5600-LABEL: name: udiv_v4u32
337    ; P5600: liveins: $a0, $a1, $a2
338    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
339    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
340    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
341    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
342    ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
343    ; P5600: [[DIV_U_W:%[0-9]+]]:msa128w = DIV_U_W [[LD_W]], [[LD_W1]]
344    ; P5600: ST_W [[DIV_U_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
345    ; P5600: RetRA
346    %0:gprb(p0) = COPY $a0
347    %1:gprb(p0) = COPY $a1
348    %2:gprb(p0) = COPY $a2
349    %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
350    %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
351    %5:fprb(<4 x s32>) = G_UDIV %3, %4
352    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
353    RetRA
354
355...
356---
357name:            udiv_v2u64
358alignment:       4
359legalized:       true
360regBankSelected: true
361tracksRegLiveness: true
362body:             |
363  bb.1.entry:
364    liveins: $a0, $a1, $a2
365
366    ; P5600-LABEL: name: udiv_v2u64
367    ; P5600: liveins: $a0, $a1, $a2
368    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
369    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
370    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
371    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
372    ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
373    ; P5600: [[DIV_U_D:%[0-9]+]]:msa128d = DIV_U_D [[LD_D]], [[LD_D1]]
374    ; P5600: ST_D [[DIV_U_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
375    ; P5600: RetRA
376    %0:gprb(p0) = COPY $a0
377    %1:gprb(p0) = COPY $a1
378    %2:gprb(p0) = COPY $a2
379    %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
380    %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
381    %5:fprb(<2 x s64>) = G_UDIV %3, %4
382    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
383    RetRA
384
385...
386---
387name:            urem_v16u8
388alignment:       4
389legalized:       true
390regBankSelected: true
391tracksRegLiveness: true
392body:             |
393  bb.1.entry:
394    liveins: $a0, $a1, $a2
395
396    ; P5600-LABEL: name: urem_v16u8
397    ; P5600: liveins: $a0, $a1, $a2
398    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
399    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
400    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
401    ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load (<16 x s8>) from %ir.a)
402    ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load (<16 x s8>) from %ir.b)
403    ; P5600: [[MOD_U_B:%[0-9]+]]:msa128b = MOD_U_B [[LD_B]], [[LD_B1]]
404    ; P5600: ST_B [[MOD_U_B]], [[COPY2]], 0 :: (store (<16 x s8>) into %ir.c)
405    ; P5600: RetRA
406    %0:gprb(p0) = COPY $a0
407    %1:gprb(p0) = COPY $a1
408    %2:gprb(p0) = COPY $a2
409    %3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
410    %4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
411    %5:fprb(<16 x s8>) = G_UREM %3, %4
412    G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)
413    RetRA
414
415...
416---
417name:            urem_v8u16
418alignment:       4
419legalized:       true
420regBankSelected: true
421tracksRegLiveness: true
422body:             |
423  bb.1.entry:
424    liveins: $a0, $a1, $a2
425
426    ; P5600-LABEL: name: urem_v8u16
427    ; P5600: liveins: $a0, $a1, $a2
428    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
429    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
430    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
431    ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load (<8 x s16>) from %ir.a)
432    ; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load (<8 x s16>) from %ir.b)
433    ; P5600: [[MOD_U_H:%[0-9]+]]:msa128h = MOD_U_H [[LD_H]], [[LD_H1]]
434    ; P5600: ST_H [[MOD_U_H]], [[COPY2]], 0 :: (store (<8 x s16>) into %ir.c)
435    ; P5600: RetRA
436    %0:gprb(p0) = COPY $a0
437    %1:gprb(p0) = COPY $a1
438    %2:gprb(p0) = COPY $a2
439    %3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
440    %4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
441    %5:fprb(<8 x s16>) = G_UREM %3, %4
442    G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)
443    RetRA
444
445...
446---
447name:            urem_v4u32
448alignment:       4
449legalized:       true
450regBankSelected: true
451tracksRegLiveness: true
452body:             |
453  bb.1.entry:
454    liveins: $a0, $a1, $a2
455
456    ; P5600-LABEL: name: urem_v4u32
457    ; P5600: liveins: $a0, $a1, $a2
458    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
459    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
460    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
461    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
462    ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
463    ; P5600: [[MOD_U_W:%[0-9]+]]:msa128w = MOD_U_W [[LD_W]], [[LD_W1]]
464    ; P5600: ST_W [[MOD_U_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
465    ; P5600: RetRA
466    %0:gprb(p0) = COPY $a0
467    %1:gprb(p0) = COPY $a1
468    %2:gprb(p0) = COPY $a2
469    %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
470    %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
471    %5:fprb(<4 x s32>) = G_UREM %3, %4
472    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
473    RetRA
474
475...
476---
477name:            urem_v2u64
478alignment:       4
479legalized:       true
480regBankSelected: true
481tracksRegLiveness: true
482body:             |
483  bb.1.entry:
484    liveins: $a0, $a1, $a2
485
486    ; P5600-LABEL: name: urem_v2u64
487    ; P5600: liveins: $a0, $a1, $a2
488    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
489    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
490    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
491    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
492    ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
493    ; P5600: [[MOD_U_D:%[0-9]+]]:msa128d = MOD_U_D [[LD_D]], [[LD_D1]]
494    ; P5600: ST_D [[MOD_U_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
495    ; P5600: RetRA
496    %0:gprb(p0) = COPY $a0
497    %1:gprb(p0) = COPY $a1
498    %2:gprb(p0) = COPY $a2
499    %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
500    %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
501    %5:fprb(<2 x s64>) = G_UREM %3, %4
502    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
503    RetRA
504
505...
506