xref: /llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir (revision 60442f0d442723a487528bdd8b48b24657a025e8)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
3--- |
4
5  define void @mul_i32(i32 %x, i32 %y) {entry: ret void}
6  define void @umul_with_overflow(i32 %lhs, i32 %rhs, ptr %pmul, ptr %pcarry_flag) { ret void }
7
8...
9---
10name:            mul_i32
11alignment:       4
12legalized:       true
13regBankSelected: true
14tracksRegLiveness: true
15body:             |
16  bb.0.entry:
17    liveins: $a0, $a1
18
19    ; MIPS32-LABEL: name: mul_i32
20    ; MIPS32: liveins: $a0, $a1
21    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
22    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
23    ; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def dead $hi0, implicit-def dead $lo0
24    ; MIPS32: $v0 = COPY [[MUL]]
25    ; MIPS32: RetRA implicit $v0
26    %0:gprb(s32) = COPY $a0
27    %1:gprb(s32) = COPY $a1
28    %2:gprb(s32) = G_MUL %0, %1
29    $v0 = COPY %2(s32)
30    RetRA implicit $v0
31
32...
33---
34name:            umul_with_overflow
35alignment:       4
36legalized:       true
37regBankSelected: true
38tracksRegLiveness: true
39body:             |
40  bb.1 (%ir-block.0):
41    liveins: $a0, $a1, $a2, $a3
42
43    ; MIPS32-LABEL: name: umul_with_overflow
44    ; MIPS32: liveins: $a0, $a1, $a2, $a3
45    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
46    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
47    ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
48    ; MIPS32: [[COPY3:%[0-9]+]]:gpr32 = COPY $a3
49    ; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def dead $hi0, implicit-def dead $lo0
50    ; MIPS32: [[PseudoMULTu:%[0-9]+]]:acc64 = PseudoMULTu [[COPY]], [[COPY1]]
51    ; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoMULTu]]
52    ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[PseudoMFHI]]
53    ; MIPS32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1
54    ; MIPS32: SB [[ANDi]], [[COPY3]], 0 :: (store (s8) into %ir.pcarry_flag)
55    ; MIPS32: SW [[MUL]], [[COPY2]], 0 :: (store (s32) into %ir.pmul)
56    ; MIPS32: RetRA
57    %0:gprb(s32) = COPY $a0
58    %1:gprb(s32) = COPY $a1
59    %2:gprb(p0) = COPY $a2
60    %3:gprb(p0) = COPY $a3
61    %4:gprb(s32) = G_MUL %0, %1
62    %7:gprb(s32) = G_UMULH %0, %1
63    %8:gprb(s32) = G_CONSTANT i32 0
64    %9:gprb(s32) = G_ICMP intpred(ne), %7(s32), %8
65    %10:gprb(s32) = G_CONSTANT i32 1
66    %11:gprb(s32) = COPY %9(s32)
67    %6:gprb(s32) = G_AND %11, %10
68    G_STORE %6(s32), %3(p0) :: (store (s8) into %ir.pcarry_flag)
69    G_STORE %4(s32), %2(p0) :: (store (s32) into %ir.pmul)
70    RetRA
71
72...
73