1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=msa,+fp64 -mattr=nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600 3--- | 4 5 define void @load_store_v16i8(ptr %a, ptr %b) { entry: ret void } 6 define void @load_store_v8i16(ptr %a, ptr %b) { entry: ret void } 7 define void @load_store_v4i32(ptr %a, ptr %b) { entry: ret void } 8 define void @load_store_v2i64(ptr %a, ptr %b) { entry: ret void } 9 define void @load_store_v4f32(ptr %a, ptr %b) { entry: ret void } 10 define void @load_store_v2f64(ptr %a, ptr %b) { entry: ret void } 11 12... 13--- 14name: load_store_v16i8 15alignment: 4 16legalized: true 17regBankSelected: true 18tracksRegLiveness: true 19body: | 20 bb.1.entry: 21 liveins: $a0, $a1 22 23 ; P5600-LABEL: name: load_store_v16i8 24 ; P5600: liveins: $a0, $a1 25 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 26 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 27 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load (<16 x s8>) from %ir.b) 28 ; P5600: ST_B [[LD_B]], [[COPY]], 0 :: (store (<16 x s8>) into %ir.a) 29 ; P5600: RetRA 30 %0:gprb(p0) = COPY $a0 31 %1:gprb(p0) = COPY $a1 32 %2:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b) 33 G_STORE %2(<16 x s8>), %0(p0) :: (store (<16 x s8>) into %ir.a) 34 RetRA 35 36... 37--- 38name: load_store_v8i16 39alignment: 4 40legalized: true 41regBankSelected: true 42tracksRegLiveness: true 43body: | 44 bb.1.entry: 45 liveins: $a0, $a1 46 47 ; P5600-LABEL: name: load_store_v8i16 48 ; P5600: liveins: $a0, $a1 49 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 50 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 51 ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load (<8 x s16>) from %ir.b) 52 ; P5600: ST_H [[LD_H]], [[COPY]], 0 :: (store (<8 x s16>) into %ir.a) 53 ; P5600: RetRA 54 %0:gprb(p0) = COPY $a0 55 %1:gprb(p0) = COPY $a1 56 %2:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b) 57 G_STORE %2(<8 x s16>), %0(p0) :: (store (<8 x s16>) into %ir.a) 58 RetRA 59 60... 61--- 62name: load_store_v4i32 63alignment: 4 64legalized: true 65regBankSelected: true 66tracksRegLiveness: true 67body: | 68 bb.1.entry: 69 liveins: $a0, $a1 70 71 ; P5600-LABEL: name: load_store_v4i32 72 ; P5600: liveins: $a0, $a1 73 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 74 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 75 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b) 76 ; P5600: ST_W [[LD_W]], [[COPY]], 0 :: (store (<4 x s32>) into %ir.a) 77 ; P5600: RetRA 78 %0:gprb(p0) = COPY $a0 79 %1:gprb(p0) = COPY $a1 80 %2:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b) 81 G_STORE %2(<4 x s32>), %0(p0) :: (store (<4 x s32>) into %ir.a) 82 RetRA 83 84... 85--- 86name: load_store_v2i64 87alignment: 4 88legalized: true 89regBankSelected: true 90tracksRegLiveness: true 91body: | 92 bb.1.entry: 93 liveins: $a0, $a1 94 95 ; P5600-LABEL: name: load_store_v2i64 96 ; P5600: liveins: $a0, $a1 97 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 98 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 99 ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b) 100 ; P5600: ST_D [[LD_D]], [[COPY]], 0 :: (store (<2 x s64>) into %ir.a) 101 ; P5600: RetRA 102 %0:gprb(p0) = COPY $a0 103 %1:gprb(p0) = COPY $a1 104 %2:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b) 105 G_STORE %2(<2 x s64>), %0(p0) :: (store (<2 x s64>) into %ir.a) 106 RetRA 107 108... 109--- 110name: load_store_v4f32 111alignment: 4 112legalized: true 113regBankSelected: true 114tracksRegLiveness: true 115body: | 116 bb.1.entry: 117 liveins: $a0, $a1 118 119 ; P5600-LABEL: name: load_store_v4f32 120 ; P5600: liveins: $a0, $a1 121 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 122 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 123 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b) 124 ; P5600: ST_W [[LD_W]], [[COPY]], 0 :: (store (<4 x s32>) into %ir.a) 125 ; P5600: RetRA 126 %0:gprb(p0) = COPY $a0 127 %1:gprb(p0) = COPY $a1 128 %2:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b) 129 G_STORE %2(<4 x s32>), %0(p0) :: (store (<4 x s32>) into %ir.a) 130 RetRA 131 132... 133--- 134name: load_store_v2f64 135alignment: 4 136legalized: true 137regBankSelected: true 138tracksRegLiveness: true 139body: | 140 bb.1.entry: 141 liveins: $a0, $a1 142 143 ; P5600-LABEL: name: load_store_v2f64 144 ; P5600: liveins: $a0, $a1 145 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 146 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 147 ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b) 148 ; P5600: ST_D [[LD_D]], [[COPY]], 0 :: (store (<2 x s64>) into %ir.a) 149 ; P5600: RetRA 150 %0:gprb(p0) = COPY $a0 151 %1:gprb(p0) = COPY $a1 152 %2:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b) 153 G_STORE %2(<2 x s64>), %0(p0) :: (store (<2 x s64>) into %ir.a) 154 RetRA 155 156... 157