xref: /llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_4_unaligned_r6.mir (revision 60442f0d442723a487528bdd8b48b24657a025e8) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
3--- |
4
5  @float_align1 = common global float 0.000000e+00, align 1
6  @float_align8 = common global float 0.000000e+00, align 8
7  @i32_align2 = common global i32 0, align 2
8
9  define float @load_float_align1() {
10  entry:
11    %0 = load float, ptr @float_align1, align 1
12    ret float %0
13  }
14
15  define float @load_float_align8() {
16  entry:
17    %0 = load float, ptr @float_align8, align 8
18    ret float %0
19  }
20
21  define i32 @load_i32_align2() {
22  entry:
23    %0 = load i32, ptr @i32_align2, align 2
24    ret i32 %0
25  }
26
27...
28---
29name:            load_float_align1
30alignment:       4
31legalized:       true
32regBankSelected: true
33tracksRegLiveness: true
34body:             |
35  bb.1.entry:
36
37    ; MIPS32R6-LABEL: name: load_float_align1
38    ; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1
39    ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
40    ; MIPS32R6: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[ADDiu]], 0 :: (dereferenceable load (s32) from @float_align1, align 1)
41    ; MIPS32R6: $f0 = COPY [[LWC1_]]
42    ; MIPS32R6: RetRA implicit $f0
43    %1:gprb(p0) = G_GLOBAL_VALUE @float_align1
44    %0:fprb(s32) = G_LOAD %1(p0) :: (dereferenceable load (s32) from @float_align1, align 1)
45    $f0 = COPY %0(s32)
46    RetRA implicit $f0
47
48...
49---
50name:            load_float_align8
51alignment:       4
52legalized:       true
53regBankSelected: true
54tracksRegLiveness: true
55body:             |
56  bb.1.entry:
57
58    ; MIPS32R6-LABEL: name: load_float_align8
59    ; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align8
60    ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align8
61    ; MIPS32R6: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[ADDiu]], 0 :: (dereferenceable load (s32) from @float_align8, align 8)
62    ; MIPS32R6: $f0 = COPY [[LWC1_]]
63    ; MIPS32R6: RetRA implicit $f0
64    %1:gprb(p0) = G_GLOBAL_VALUE @float_align8
65    %0:fprb(s32) = G_LOAD %1(p0) :: (dereferenceable load (s32) from @float_align8, align 8)
66    $f0 = COPY %0(s32)
67    RetRA implicit $f0
68
69...
70---
71name:            load_i32_align2
72alignment:       4
73legalized:       true
74regBankSelected: true
75tracksRegLiveness: true
76body:             |
77  bb.1.entry:
78
79    ; MIPS32R6-LABEL: name: load_i32_align2
80    ; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align2
81    ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align2
82    ; MIPS32R6: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (dereferenceable load (s32) from @i32_align2, align 2)
83    ; MIPS32R6: $v0 = COPY [[LW]]
84    ; MIPS32R6: RetRA implicit $v0
85    %1:gprb(p0) = G_GLOBAL_VALUE @i32_align2
86    %0:gprb(s32) = G_LOAD %1(p0) :: (dereferenceable load (s32) from @i32_align2, align 2)
87    $v0 = COPY %0(s32)
88    RetRA implicit $v0
89
90...
91