1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 3# RUN: llc -O0 -mtriple=mipsel-linux-gnu -relocation-model=pic -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32_PIC 4--- | 5 6 define i32 @mod4_0_to_11(i32 %a) { 7 entry: 8 switch i32 %a, label %sw.default [ 9 i32 0, label %sw.bb 10 i32 4, label %sw.bb 11 i32 1, label %sw.bb1 12 i32 5, label %sw.bb1 13 i32 2, label %sw.bb2 14 i32 6, label %sw.bb2 15 i32 3, label %sw.bb3 16 i32 7, label %sw.bb3 17 ] 18 19 sw.bb: ; preds = %entry, %entry 20 ret i32 0 21 22 sw.bb1: ; preds = %entry, %entry 23 ret i32 1 24 25 sw.bb2: ; preds = %entry, %entry 26 ret i32 2 27 28 sw.bb3: ; preds = %entry, %entry 29 ret i32 3 30 31 sw.default: ; preds = %entry 32 br label %sw.epilog 33 34 sw.epilog: ; preds = %sw.default 35 switch i32 %a, label %sw.default8 [ 36 i32 8, label %sw.bb4 37 i32 9, label %sw.bb5 38 i32 10, label %sw.bb6 39 i32 11, label %sw.bb7 40 ] 41 42 sw.bb4: ; preds = %sw.epilog 43 ret i32 0 44 45 sw.bb5: ; preds = %sw.epilog 46 ret i32 1 47 48 sw.bb6: ; preds = %sw.epilog 49 ret i32 2 50 51 sw.bb7: ; preds = %sw.epilog 52 ret i32 3 53 54 sw.default8: ; preds = %sw.epilog 55 ret i32 -1 56 } 57 58... 59--- 60name: mod4_0_to_11 61alignment: 4 62legalized: true 63regBankSelected: true 64tracksRegLiveness: true 65jumpTable: 66 kind: block-address 67 entries: 68 - id: 0 69 blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.2', '%bb.3', 70 '%bb.4', '%bb.5' ] 71 - id: 1 72 blocks: [ '%bb.8', '%bb.9', '%bb.10', '%bb.11' ] 73body: | 74 ; MIPS32-LABEL: name: mod4_0_to_11 75 ; MIPS32: bb.0.entry: 76 ; MIPS32-NEXT: successors: %bb.6(0x40000000), %bb.1(0x40000000) 77 ; MIPS32-NEXT: liveins: $a0 78 ; MIPS32-NEXT: {{ $}} 79 ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 80 ; MIPS32-NEXT: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 7 81 ; MIPS32-NEXT: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3 82 ; MIPS32-NEXT: [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 2 83 ; MIPS32-NEXT: [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 1 84 ; MIPS32-NEXT: [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 0 85 ; MIPS32-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535 86 ; MIPS32-NEXT: [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0 87 ; MIPS32-NEXT: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]] 88 ; MIPS32-NEXT: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]] 89 ; MIPS32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1 90 ; MIPS32-NEXT: BNE [[ANDi]], $zero, %bb.6, implicit-def dead $at 91 ; MIPS32-NEXT: {{ $}} 92 ; MIPS32-NEXT: bb.1.entry: 93 ; MIPS32-NEXT: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000) 94 ; MIPS32-NEXT: {{ $}} 95 ; MIPS32-NEXT: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.0 96 ; MIPS32-NEXT: [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 2 97 ; MIPS32-NEXT: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[LUi]], [[SLL]] 98 ; MIPS32-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-abs-lo) %jump-table.0 :: (load (s32)) 99 ; MIPS32-NEXT: PseudoIndirectBranch [[LW]] 100 ; MIPS32-NEXT: {{ $}} 101 ; MIPS32-NEXT: bb.2.sw.bb: 102 ; MIPS32-NEXT: $v0 = COPY [[ORi4]] 103 ; MIPS32-NEXT: RetRA implicit $v0 104 ; MIPS32-NEXT: {{ $}} 105 ; MIPS32-NEXT: bb.3.sw.bb1: 106 ; MIPS32-NEXT: $v0 = COPY [[ORi3]] 107 ; MIPS32-NEXT: RetRA implicit $v0 108 ; MIPS32-NEXT: {{ $}} 109 ; MIPS32-NEXT: bb.4.sw.bb2: 110 ; MIPS32-NEXT: $v0 = COPY [[ORi2]] 111 ; MIPS32-NEXT: RetRA implicit $v0 112 ; MIPS32-NEXT: {{ $}} 113 ; MIPS32-NEXT: bb.5.sw.bb3: 114 ; MIPS32-NEXT: $v0 = COPY [[ORi1]] 115 ; MIPS32-NEXT: RetRA implicit $v0 116 ; MIPS32-NEXT: {{ $}} 117 ; MIPS32-NEXT: bb.6.sw.default: 118 ; MIPS32-NEXT: successors: %bb.7(0x80000000) 119 ; MIPS32-NEXT: {{ $}} 120 ; MIPS32-NEXT: bb.7.sw.epilog: 121 ; MIPS32-NEXT: successors: %bb.13(0x40000000), %bb.8(0x40000000) 122 ; MIPS32-NEXT: {{ $}} 123 ; MIPS32-NEXT: [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8 124 ; MIPS32-NEXT: [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]] 125 ; MIPS32-NEXT: [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]] 126 ; MIPS32-NEXT: [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1 127 ; MIPS32-NEXT: BNE [[ANDi1]], $zero, %bb.13, implicit-def dead $at 128 ; MIPS32-NEXT: {{ $}} 129 ; MIPS32-NEXT: bb.8.sw.epilog: 130 ; MIPS32-NEXT: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000) 131 ; MIPS32-NEXT: {{ $}} 132 ; MIPS32-NEXT: [[LUi1:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.1 133 ; MIPS32-NEXT: [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2 134 ; MIPS32-NEXT: [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LUi1]], [[SLL1]] 135 ; MIPS32-NEXT: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDu1]], target-flags(mips-abs-lo) %jump-table.1 :: (load (s32)) 136 ; MIPS32-NEXT: PseudoIndirectBranch [[LW1]] 137 ; MIPS32-NEXT: {{ $}} 138 ; MIPS32-NEXT: bb.9.sw.bb4: 139 ; MIPS32-NEXT: $v0 = COPY [[ORi4]] 140 ; MIPS32-NEXT: RetRA implicit $v0 141 ; MIPS32-NEXT: {{ $}} 142 ; MIPS32-NEXT: bb.10.sw.bb5: 143 ; MIPS32-NEXT: $v0 = COPY [[ORi3]] 144 ; MIPS32-NEXT: RetRA implicit $v0 145 ; MIPS32-NEXT: {{ $}} 146 ; MIPS32-NEXT: bb.11.sw.bb6: 147 ; MIPS32-NEXT: $v0 = COPY [[ORi2]] 148 ; MIPS32-NEXT: RetRA implicit $v0 149 ; MIPS32-NEXT: {{ $}} 150 ; MIPS32-NEXT: bb.12.sw.bb7: 151 ; MIPS32-NEXT: $v0 = COPY [[ORi1]] 152 ; MIPS32-NEXT: RetRA implicit $v0 153 ; MIPS32-NEXT: {{ $}} 154 ; MIPS32-NEXT: bb.13.sw.default8: 155 ; MIPS32-NEXT: $v0 = COPY [[ADDiu]] 156 ; MIPS32-NEXT: RetRA implicit $v0 157 ; 158 ; MIPS32_PIC-LABEL: name: mod4_0_to_11 159 ; MIPS32_PIC: bb.0.entry: 160 ; MIPS32_PIC-NEXT: successors: %bb.6(0x40000000), %bb.1(0x40000000) 161 ; MIPS32_PIC-NEXT: liveins: $a0, $t9, $v0 162 ; MIPS32_PIC-NEXT: {{ $}} 163 ; MIPS32_PIC-NEXT: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9 164 ; MIPS32_PIC-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 165 ; MIPS32_PIC-NEXT: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 7 166 ; MIPS32_PIC-NEXT: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3 167 ; MIPS32_PIC-NEXT: [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 2 168 ; MIPS32_PIC-NEXT: [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 1 169 ; MIPS32_PIC-NEXT: [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 0 170 ; MIPS32_PIC-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535 171 ; MIPS32_PIC-NEXT: [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0 172 ; MIPS32_PIC-NEXT: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]] 173 ; MIPS32_PIC-NEXT: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]] 174 ; MIPS32_PIC-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1 175 ; MIPS32_PIC-NEXT: BNE [[ANDi]], $zero, %bb.6, implicit-def dead $at 176 ; MIPS32_PIC-NEXT: {{ $}} 177 ; MIPS32_PIC-NEXT: bb.1.entry: 178 ; MIPS32_PIC-NEXT: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000) 179 ; MIPS32_PIC-NEXT: {{ $}} 180 ; MIPS32_PIC-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.0 :: (load (s32) from got) 181 ; MIPS32_PIC-NEXT: [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 2 182 ; MIPS32_PIC-NEXT: [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LW]], [[SLL]] 183 ; MIPS32_PIC-NEXT: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDu1]], target-flags(mips-abs-lo) %jump-table.0 :: (load (s32)) 184 ; MIPS32_PIC-NEXT: [[ADDu2:%[0-9]+]]:gpr32 = ADDu [[LW1]], [[ADDu]] 185 ; MIPS32_PIC-NEXT: PseudoIndirectBranch [[ADDu2]] 186 ; MIPS32_PIC-NEXT: {{ $}} 187 ; MIPS32_PIC-NEXT: bb.2.sw.bb: 188 ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi4]] 189 ; MIPS32_PIC-NEXT: RetRA implicit $v0 190 ; MIPS32_PIC-NEXT: {{ $}} 191 ; MIPS32_PIC-NEXT: bb.3.sw.bb1: 192 ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi3]] 193 ; MIPS32_PIC-NEXT: RetRA implicit $v0 194 ; MIPS32_PIC-NEXT: {{ $}} 195 ; MIPS32_PIC-NEXT: bb.4.sw.bb2: 196 ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi2]] 197 ; MIPS32_PIC-NEXT: RetRA implicit $v0 198 ; MIPS32_PIC-NEXT: {{ $}} 199 ; MIPS32_PIC-NEXT: bb.5.sw.bb3: 200 ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi1]] 201 ; MIPS32_PIC-NEXT: RetRA implicit $v0 202 ; MIPS32_PIC-NEXT: {{ $}} 203 ; MIPS32_PIC-NEXT: bb.6.sw.default: 204 ; MIPS32_PIC-NEXT: successors: %bb.7(0x80000000) 205 ; MIPS32_PIC-NEXT: {{ $}} 206 ; MIPS32_PIC-NEXT: bb.7.sw.epilog: 207 ; MIPS32_PIC-NEXT: successors: %bb.13(0x40000000), %bb.8(0x40000000) 208 ; MIPS32_PIC-NEXT: {{ $}} 209 ; MIPS32_PIC-NEXT: [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8 210 ; MIPS32_PIC-NEXT: [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]] 211 ; MIPS32_PIC-NEXT: [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]] 212 ; MIPS32_PIC-NEXT: [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1 213 ; MIPS32_PIC-NEXT: BNE [[ANDi1]], $zero, %bb.13, implicit-def dead $at 214 ; MIPS32_PIC-NEXT: {{ $}} 215 ; MIPS32_PIC-NEXT: bb.8.sw.epilog: 216 ; MIPS32_PIC-NEXT: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000) 217 ; MIPS32_PIC-NEXT: {{ $}} 218 ; MIPS32_PIC-NEXT: [[LW2:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.1 :: (load (s32) from got) 219 ; MIPS32_PIC-NEXT: [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2 220 ; MIPS32_PIC-NEXT: [[ADDu3:%[0-9]+]]:gpr32 = ADDu [[LW2]], [[SLL1]] 221 ; MIPS32_PIC-NEXT: [[LW3:%[0-9]+]]:gpr32 = LW [[ADDu3]], target-flags(mips-abs-lo) %jump-table.1 :: (load (s32)) 222 ; MIPS32_PIC-NEXT: [[ADDu4:%[0-9]+]]:gpr32 = ADDu [[LW3]], [[ADDu]] 223 ; MIPS32_PIC-NEXT: PseudoIndirectBranch [[ADDu4]] 224 ; MIPS32_PIC-NEXT: {{ $}} 225 ; MIPS32_PIC-NEXT: bb.9.sw.bb4: 226 ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi4]] 227 ; MIPS32_PIC-NEXT: RetRA implicit $v0 228 ; MIPS32_PIC-NEXT: {{ $}} 229 ; MIPS32_PIC-NEXT: bb.10.sw.bb5: 230 ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi3]] 231 ; MIPS32_PIC-NEXT: RetRA implicit $v0 232 ; MIPS32_PIC-NEXT: {{ $}} 233 ; MIPS32_PIC-NEXT: bb.11.sw.bb6: 234 ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi2]] 235 ; MIPS32_PIC-NEXT: RetRA implicit $v0 236 ; MIPS32_PIC-NEXT: {{ $}} 237 ; MIPS32_PIC-NEXT: bb.12.sw.bb7: 238 ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi1]] 239 ; MIPS32_PIC-NEXT: RetRA implicit $v0 240 ; MIPS32_PIC-NEXT: {{ $}} 241 ; MIPS32_PIC-NEXT: bb.13.sw.default8: 242 ; MIPS32_PIC-NEXT: $v0 = COPY [[ADDiu]] 243 ; MIPS32_PIC-NEXT: RetRA implicit $v0 244 bb.1.entry: 245 liveins: $a0 246 247 %0:gprb(s32) = COPY $a0 248 %4:gprb(s32) = G_CONSTANT i32 7 249 %8:gprb(s32) = G_CONSTANT i32 3 250 %9:gprb(s32) = G_CONSTANT i32 2 251 %10:gprb(s32) = G_CONSTANT i32 1 252 %11:gprb(s32) = G_CONSTANT i32 0 253 %18:gprb(s32) = G_CONSTANT i32 -1 254 %1:gprb(s32) = G_CONSTANT i32 0 255 %2:gprb(s32) = G_SUB %0, %1 256 %3:gprb(s32) = COPY %2(s32) 257 %5:gprb(s32) = COPY %4(s32) 258 %22:gprb(s32) = G_ICMP intpred(ugt), %3(s32), %5 259 %23:gprb(s32) = COPY %22(s32) 260 %21:gprb(s32) = G_AND %23, %10 261 G_BRCOND %21(s32), %bb.6 262 263 bb.13.entry: 264 successors: %bb.2, %bb.3, %bb.4, %bb.5 265 266 %7:gprb(p0) = G_JUMP_TABLE %jump-table.0 267 G_BRJT %7(p0), %jump-table.0, %3(s32) 268 269 bb.2.sw.bb: 270 $v0 = COPY %11(s32) 271 RetRA implicit $v0 272 273 bb.3.sw.bb1: 274 $v0 = COPY %10(s32) 275 RetRA implicit $v0 276 277 bb.4.sw.bb2: 278 $v0 = COPY %9(s32) 279 RetRA implicit $v0 280 281 bb.5.sw.bb3: 282 $v0 = COPY %8(s32) 283 RetRA implicit $v0 284 285 bb.6.sw.default: 286 287 bb.7.sw.epilog: 288 %12:gprb(s32) = G_CONSTANT i32 8 289 %13:gprb(s32) = G_SUB %0, %12 290 %14:gprb(s32) = COPY %13(s32) 291 %15:gprb(s32) = COPY %8(s32) 292 %20:gprb(s32) = G_ICMP intpred(ugt), %14(s32), %15 293 %24:gprb(s32) = G_CONSTANT i32 1 294 %25:gprb(s32) = COPY %20(s32) 295 %19:gprb(s32) = G_AND %25, %24 296 G_BRCOND %19(s32), %bb.12 297 298 bb.14.sw.epilog: 299 successors: %bb.8, %bb.9, %bb.10, %bb.11 300 301 %17:gprb(p0) = G_JUMP_TABLE %jump-table.1 302 G_BRJT %17(p0), %jump-table.1, %14(s32) 303 304 bb.8.sw.bb4: 305 $v0 = COPY %11(s32) 306 RetRA implicit $v0 307 308 bb.9.sw.bb5: 309 $v0 = COPY %10(s32) 310 RetRA implicit $v0 311 312 bb.10.sw.bb6: 313 $v0 = COPY %9(s32) 314 RetRA implicit $v0 315 316 bb.11.sw.bb7: 317 $v0 = COPY %8(s32) 318 RetRA implicit $v0 319 320 bb.12.sw.default8: 321 $v0 = COPY %18(s32) 322 RetRA implicit $v0 323 324... 325