1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
3--- |
4
5  define void @fadd_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
6  define void @fadd_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }
7
8  define void @fsub_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
9  define void @fsub_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }
10
11  define void @fmul_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
12  define void @fmul_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }
13
14  define void @fdiv_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
15  define void @fdiv_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }
16
17...
18---
19name:            fadd_v4f32
20alignment:       4
21legalized:       true
22regBankSelected: true
23tracksRegLiveness: true
24body:             |
25  bb.1.entry:
26    liveins: $a0, $a1, $a2
27
28    ; P5600-LABEL: name: fadd_v4f32
29    ; P5600: liveins: $a0, $a1, $a2
30    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
31    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
32    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
33    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
34    ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
35    ; P5600: [[FADD_W:%[0-9]+]]:msa128w = FADD_W [[LD_W]], [[LD_W1]]
36    ; P5600: ST_W [[FADD_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
37    ; P5600: RetRA
38    %0:gprb(p0) = COPY $a0
39    %1:gprb(p0) = COPY $a1
40    %2:gprb(p0) = COPY $a2
41    %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
42    %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
43    %5:fprb(<4 x s32>) = G_FADD %3, %4
44    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
45    RetRA
46
47...
48---
49name:            fadd_v2f64
50alignment:       4
51legalized:       true
52regBankSelected: true
53tracksRegLiveness: true
54body:             |
55  bb.1.entry:
56    liveins: $a0, $a1, $a2
57
58    ; P5600-LABEL: name: fadd_v2f64
59    ; P5600: liveins: $a0, $a1, $a2
60    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
61    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
62    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
63    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
64    ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
65    ; P5600: [[FADD_D:%[0-9]+]]:msa128d = FADD_D [[LD_D]], [[LD_D1]]
66    ; P5600: ST_D [[FADD_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
67    ; P5600: RetRA
68    %0:gprb(p0) = COPY $a0
69    %1:gprb(p0) = COPY $a1
70    %2:gprb(p0) = COPY $a2
71    %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
72    %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
73    %5:fprb(<2 x s64>) = G_FADD %3, %4
74    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
75    RetRA
76
77...
78---
79name:            fsub_v4f32
80alignment:       4
81legalized:       true
82regBankSelected: true
83tracksRegLiveness: true
84body:             |
85  bb.1.entry:
86    liveins: $a0, $a1, $a2
87
88    ; P5600-LABEL: name: fsub_v4f32
89    ; P5600: liveins: $a0, $a1, $a2
90    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
91    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
92    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
93    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
94    ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
95    ; P5600: [[FSUB_W:%[0-9]+]]:msa128w = FSUB_W [[LD_W]], [[LD_W1]]
96    ; P5600: ST_W [[FSUB_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
97    ; P5600: RetRA
98    %0:gprb(p0) = COPY $a0
99    %1:gprb(p0) = COPY $a1
100    %2:gprb(p0) = COPY $a2
101    %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
102    %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
103    %5:fprb(<4 x s32>) = G_FSUB %3, %4
104    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
105    RetRA
106
107...
108---
109name:            fsub_v2f64
110alignment:       4
111legalized:       true
112regBankSelected: true
113tracksRegLiveness: true
114body:             |
115  bb.1.entry:
116    liveins: $a0, $a1, $a2
117
118    ; P5600-LABEL: name: fsub_v2f64
119    ; P5600: liveins: $a0, $a1, $a2
120    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
121    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
122    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
123    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
124    ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
125    ; P5600: [[FSUB_D:%[0-9]+]]:msa128d = FSUB_D [[LD_D]], [[LD_D1]]
126    ; P5600: ST_D [[FSUB_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
127    ; P5600: RetRA
128    %0:gprb(p0) = COPY $a0
129    %1:gprb(p0) = COPY $a1
130    %2:gprb(p0) = COPY $a2
131    %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
132    %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
133    %5:fprb(<2 x s64>) = G_FSUB %3, %4
134    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
135    RetRA
136
137...
138---
139name:            fmul_v4f32
140alignment:       4
141legalized:       true
142regBankSelected: true
143tracksRegLiveness: true
144body:             |
145  bb.1.entry:
146    liveins: $a0, $a1, $a2
147
148    ; P5600-LABEL: name: fmul_v4f32
149    ; P5600: liveins: $a0, $a1, $a2
150    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
151    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
152    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
153    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
154    ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
155    ; P5600: [[FMUL_W:%[0-9]+]]:msa128w = FMUL_W [[LD_W]], [[LD_W1]]
156    ; P5600: ST_W [[FMUL_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
157    ; P5600: RetRA
158    %0:gprb(p0) = COPY $a0
159    %1:gprb(p0) = COPY $a1
160    %2:gprb(p0) = COPY $a2
161    %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
162    %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
163    %5:fprb(<4 x s32>) = G_FMUL %3, %4
164    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
165    RetRA
166
167...
168---
169name:            fmul_v2f64
170alignment:       4
171legalized:       true
172regBankSelected: true
173tracksRegLiveness: true
174body:             |
175  bb.1.entry:
176    liveins: $a0, $a1, $a2
177
178    ; P5600-LABEL: name: fmul_v2f64
179    ; P5600: liveins: $a0, $a1, $a2
180    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
181    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
182    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
183    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
184    ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
185    ; P5600: [[FMUL_D:%[0-9]+]]:msa128d = FMUL_D [[LD_D]], [[LD_D1]]
186    ; P5600: ST_D [[FMUL_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
187    ; P5600: RetRA
188    %0:gprb(p0) = COPY $a0
189    %1:gprb(p0) = COPY $a1
190    %2:gprb(p0) = COPY $a2
191    %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
192    %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
193    %5:fprb(<2 x s64>) = G_FMUL %3, %4
194    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
195    RetRA
196
197...
198---
199name:            fdiv_v4f32
200alignment:       4
201legalized:       true
202regBankSelected: true
203tracksRegLiveness: true
204body:             |
205  bb.1.entry:
206    liveins: $a0, $a1, $a2
207
208    ; P5600-LABEL: name: fdiv_v4f32
209    ; P5600: liveins: $a0, $a1, $a2
210    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
211    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
212    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
213    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
214    ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
215    ; P5600: [[FDIV_W:%[0-9]+]]:msa128w = FDIV_W [[LD_W]], [[LD_W1]]
216    ; P5600: ST_W [[FDIV_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
217    ; P5600: RetRA
218    %0:gprb(p0) = COPY $a0
219    %1:gprb(p0) = COPY $a1
220    %2:gprb(p0) = COPY $a2
221    %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
222    %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
223    %5:fprb(<4 x s32>) = G_FDIV %3, %4
224    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
225    RetRA
226
227...
228---
229name:            fdiv_v2f64
230alignment:       4
231legalized:       true
232regBankSelected: true
233tracksRegLiveness: true
234body:             |
235  bb.1.entry:
236    liveins: $a0, $a1, $a2
237
238    ; P5600-LABEL: name: fdiv_v2f64
239    ; P5600: liveins: $a0, $a1, $a2
240    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
241    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
242    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
243    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
244    ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
245    ; P5600: [[FDIV_D:%[0-9]+]]:msa128d = FDIV_D [[LD_D]], [[LD_D1]]
246    ; P5600: ST_D [[FDIV_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
247    ; P5600: RetRA
248    %0:gprb(p0) = COPY $a0
249    %1:gprb(p0) = COPY $a1
250    %2:gprb(p0) = COPY $a2
251    %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
252    %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
253    %5:fprb(<2 x s64>) = G_FDIV %3, %4
254    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
255    RetRA
256
257...
258