xref: /llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bswap.mir (revision 94a24e7a401be7a3db0ddfa2035855b75c8cc55d) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=instruction-select -mattr=+mips32r2 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R2
3--- |
4
5  define void @bswap_i32() { entry: ret void }
6
7...
8---
9name:            bswap_i32
10alignment:       4
11legalized:       true
12regBankSelected: true
13tracksRegLiveness: true
14body:             |
15  bb.1.entry:
16    liveins: $a0
17
18    ; MIPS32R2-LABEL: name: bswap_i32
19    ; MIPS32R2: liveins: $a0
20    ; MIPS32R2: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
21    ; MIPS32R2: [[WSBH:%[0-9]+]]:gpr32 = WSBH [[COPY]]
22    ; MIPS32R2: [[ROTR:%[0-9]+]]:gpr32 = ROTR [[WSBH]], 16
23    ; MIPS32R2: $v0 = COPY [[ROTR]]
24    ; MIPS32R2: RetRA implicit $v0
25    %0:gprb(s32) = COPY $a0
26    %1:gprb(s32) = G_BSWAP %0
27    $v0 = COPY %1(s32)
28    RetRA implicit $v0
29
30...
31