1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -O2 -relocation-model=pic \ 3; RUN: -fast-isel -fast-isel-abort=1 | FileCheck %s 4 5; FIXME: The first xor instruction is redundant. 6define i1 @sel_i1(i1 %j, i1 %k, i1 %l) { 7; CHECK-LABEL: sel_i1: 8; CHECK: # %bb.0: # %entry 9; CHECK-NEXT: xor $1, $4, $zero 10; CHECK-NEXT: andi $1, $1, 1 11; CHECK-NEXT: movn $6, $5, $1 12; CHECK-NEXT: jr $ra 13; CHECK-NEXT: move $2, $6 14entry: 15 %cond = xor i1 %j, false 16 %res = select i1 %cond, i1 %k, i1 %l 17 ret i1 %res 18} 19 20; FIXME: The seb $X, $zero and xor .., .., $x instructions are redundant. 21define i8 @sel_i8(i8 %j, i8 %k, i8 %l) { 22; CHECK-LABEL: sel_i8: 23; CHECK: # %bb.0: # %entry 24; CHECK-NEXT: seb $1, $4 25; CHECK-NEXT: seb $2, $zero 26; CHECK-NEXT: xor $1, $1, $2 27; CHECK-NEXT: sltu $1, $zero, $1 28; CHECK-NEXT: andi $1, $1, 1 29; CHECK-NEXT: movn $6, $5, $1 30; CHECK-NEXT: jr $ra 31; CHECK-NEXT: move $2, $6 32entry: 33 %cond = icmp ne i8 %j, 0 34 %res = select i1 %cond, i8 %k, i8 %l 35 ret i8 %res 36} 37 38; FIXME: The seh $X, $zero and xor .., .., $x instructions are redundant. 39define i16 @sel_i16(i16 %j, i16 %k, i16 %l) { 40; CHECK-LABEL: sel_i16: 41; CHECK: # %bb.0: # %entry 42; CHECK-NEXT: seh $1, $4 43; CHECK-NEXT: seh $2, $zero 44; CHECK-NEXT: xor $1, $1, $2 45; CHECK-NEXT: sltu $1, $zero, $1 46; CHECK-NEXT: andi $1, $1, 1 47; CHECK-NEXT: movn $6, $5, $1 48; CHECK-NEXT: jr $ra 49; CHECK-NEXT: move $2, $6 50entry: 51 %cond = icmp ne i16 %j, 0 52 %res = select i1 %cond, i16 %k, i16 %l 53 ret i16 %res 54} 55 56; FIXME: The first xor instruction is redundant. 57define i32 @sel_i32(i32 %j, i32 %k, i32 %l) { 58; CHECK-LABEL: sel_i32: 59; CHECK: # %bb.0: # %entry 60; CHECK-NEXT: xor $1, $4, $zero 61; CHECK-NEXT: sltu $1, $zero, $1 62; CHECK-NEXT: andi $1, $1, 1 63; CHECK-NEXT: movn $6, $5, $1 64; CHECK-NEXT: jr $ra 65; CHECK-NEXT: move $2, $6 66entry: 67 %cond = icmp ne i32 %j, 0 68 %res = select i1 %cond, i32 %k, i32 %l 69 ret i32 %res 70} 71 72define float @sel_float(i32 %j, float %k, float %l) { 73; CHECK-LABEL: sel_float: 74; CHECK: # %bb.0: # %entry 75; CHECK-NEXT: mtc1 $6, $f0 76; CHECK-NEXT: mtc1 $5, $f1 77; CHECK-NEXT: xor $1, $4, $zero 78; CHECK-NEXT: sltu $1, $zero, $1 79; CHECK-NEXT: andi $1, $1, 1 80; CHECK-NEXT: jr $ra 81; CHECK-NEXT: movn.s $f0, $f1, $1 82entry: 83 %cond = icmp ne i32 %j, 0 84 %res = select i1 %cond, float %k, float %l 85 ret float %res 86} 87 88define float @sel_float2(float %k, float %l, i32 %j) { 89; CHECK-LABEL: sel_float2: 90; CHECK: # %bb.0: # %entry 91; CHECK-NEXT: mov.s $f0, $f14 92; CHECK-NEXT: xor $1, $6, $zero 93; CHECK-NEXT: sltu $1, $zero, $1 94; CHECK-NEXT: andi $1, $1, 1 95; CHECK-NEXT: jr $ra 96; CHECK-NEXT: movn.s $f0, $f12, $1 97entry: 98 %cond = icmp ne i32 %j, 0 99 %res = select i1 %cond, float %k, float %l 100 ret float %res 101} 102 103define double @sel_double(i32 %j, double %k, double %l) { 104; CHECK-LABEL: sel_double: 105; CHECK: # %bb.0: # %entry 106; CHECK-NEXT: mtc1 $6, $f2 107; CHECK-NEXT: mthc1 $7, $f2 108; CHECK-NEXT: ldc1 $f0, 16($sp) 109; CHECK-NEXT: xor $1, $4, $zero 110; CHECK-NEXT: sltu $1, $zero, $1 111; CHECK-NEXT: andi $1, $1, 1 112; CHECK-NEXT: jr $ra 113; CHECK-NEXT: movn.d $f0, $f2, $1 114entry: 115 %cond = icmp ne i32 %j, 0 116 %res = select i1 %cond, double %k, double %l 117 ret double %res 118} 119 120define double @sel_double2(double %k, double %l, i32 %j) { 121; CHECK-LABEL: sel_double2: 122; CHECK: # %bb.0: # %entry 123; CHECK-NEXT: mov.d $f0, $f14 124; CHECK-NEXT: lw $1, 16($sp) 125; CHECK-NEXT: xor $1, $1, $zero 126; CHECK-NEXT: sltu $1, $zero, $1 127; CHECK-NEXT: andi $1, $1, 1 128; CHECK-NEXT: jr $ra 129; CHECK-NEXT: movn.d $f0, $f12, $1 130entry: 131 %cond = icmp ne i32 %j, 0 132 %res = select i1 %cond, double %k, double %l 133 ret double %res 134} 135