1; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \ 2; RUN: < %s -verify-machineinstrs | FileCheck %s 3 4define void @testeq(i32, i32) { 5; CHECK-LABEL: testeq: 6; CHECK: andi $[[REG0:[0-9]+]], $4, 1 7; CHECK: andi $[[REG1:[0-9]+]], $5, 1 8; CHECK: beq $[[REG0]], $[[REG1]], 9 %3 = trunc i32 %0 to i1 10 %4 = trunc i32 %1 to i1 11 %5 = icmp eq i1 %3, %4 12 br i1 %5, label %end, label %trap 13trap: 14 call void @llvm.trap() 15 br label %end 16end: 17 ret void 18} 19 20 21define void @testne(i32, i32) { 22; CHECK-LABEL: testne: 23; CHECK: andi $[[REG0:[0-9]+]], $4, 1 24; CHECK: andi $[[REG1:[0-9]+]], $5, 1 25; CHECK: bne $[[REG0]], $[[REG1]], 26 %3 = trunc i32 %0 to i1 27 %4 = trunc i32 %1 to i1 28 %5 = icmp ne i1 %3, %4 29 br i1 %5, label %end, label %trap 30trap: 31 call void @llvm.trap() 32 br label %end 33end: 34 ret void 35} 36 37 38define void @testugt(i32, i32) { 39; CHECK-LABEL: testugt: 40; CHECK: andi $[[REG0:[0-9]+]], $4, 1 41; CHECK: andi $[[REG1:[0-9]+]], $5, 1 42; CHECK: sltu $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]] 43; CHECK: bnez $[[REG2]], 44 %3 = trunc i32 %0 to i1 45 %4 = trunc i32 %1 to i1 46 %5 = icmp ugt i1 %3, %4 47 br i1 %5, label %end, label %trap 48trap: 49 call void @llvm.trap() 50 br label %end 51end: 52 ret void 53} 54 55 56define void @testuge(i32, i32) { 57; CHECK-LABEL: testuge: 58; CHECK: andi $[[REG0:[0-9]+]], $4, 1 59; CHECK: andi $[[REG1:[0-9]+]], $5, 1 60; CHECK: sltu $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]] 61; CHECK: beqz $[[REG2]], 62 %3 = trunc i32 %0 to i1 63 %4 = trunc i32 %1 to i1 64 %5 = icmp uge i1 %3, %4 65 br i1 %5, label %end, label %trap 66trap: 67 call void @llvm.trap() 68 br label %end 69end: 70 ret void 71} 72 73 74define void @testult(i32, i32) { 75; CHECK-LABEL: testult: 76; CHECK: andi $[[REG0:[0-9]+]], $4, 1 77; CHECK: andi $[[REG1:[0-9]+]], $5, 1 78; CHECK: sltu $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]] 79; CHECK: bnez $[[REG2]], 80 %3 = trunc i32 %0 to i1 81 %4 = trunc i32 %1 to i1 82 %5 = icmp ult i1 %3, %4 83 br i1 %5, label %end, label %trap 84trap: 85 call void @llvm.trap() 86 br label %end 87end: 88 ret void 89} 90 91 92define void @testule(i32, i32) { 93; CHECK: andi $[[REG0:[0-9]+]], $4, 1 94; CHECK: andi $[[REG1:[0-9]+]], $5, 1 95; CHECK: sltu $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]] 96; CHECK: beqz $[[REG2]], 97 %3 = trunc i32 %0 to i1 98 %4 = trunc i32 %1 to i1 99 %5 = icmp ule i1 %3, %4 100 br i1 %5, label %end, label %trap 101trap: 102 call void @llvm.trap() 103 br label %end 104end: 105 ret void 106} 107 108 109define void @testsgt(i32, i32) { 110; CHECK-LABEL: testsgt: 111; CHECK: andi $[[REG0:[0-9]+]], $4, 1 112; CHECK: negu $[[REG2:[0-9]+]], $[[REG0]] 113; CHECK: andi $[[REG1:[0-9]+]], $5, 1 114; CHECK: negu $[[REG3:[0-9]+]], $[[REG1]] 115; CHECK: slt $[[REG4:[0-9]+]], $[[REG3]], $[[REG2]] 116; CHECK: bnez $[[REG4]], 117 %3 = trunc i32 %0 to i1 118 %4 = trunc i32 %1 to i1 119 %5 = icmp sgt i1 %3, %4 120 br i1 %5, label %end, label %trap 121trap: 122 call void @llvm.trap() 123 br label %end 124end: 125 ret void 126} 127 128 129define void @testsge(i32, i32) { 130; CHECK-LABEL: testsge: 131; CHECK: andi $[[REG0:[0-9]+]], $4, 1 132; CHECK: negu $[[REG0]], $[[REG0]] 133; CHECK: andi $[[REG1:[0-9]+]], $5, 1 134; CHECK: negu $[[REG1]], $[[REG1]] 135; CHECK: slt $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]] 136; CHECK: beqz $[[REG2]], 137 %3 = trunc i32 %0 to i1 138 %4 = trunc i32 %1 to i1 139 %5 = icmp sge i1 %3, %4 140 br i1 %5, label %end, label %trap 141trap: 142 call void @llvm.trap() 143 br label %end 144end: 145 ret void 146} 147 148 149define void @testslt(i32, i32) { 150; CHECK-LABEL: testslt: 151; CHECK: andi $[[REG0:[0-9]+]], $4, 1 152; CHECK: negu $[[REG0]], $[[REG0]] 153; CHECK: andi $[[REG1:[0-9]+]], $5, 1 154; CHECK: negu $[[REG1]], $[[REG1]] 155; CHECK: slt $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]] 156; CHECK: bnez $[[REG2]], 157 %3 = trunc i32 %0 to i1 158 %4 = trunc i32 %1 to i1 159 %5 = icmp slt i1 %3, %4 160 br i1 %5, label %end, label %trap 161trap: 162 call void @llvm.trap() 163 br label %end 164end: 165 ret void 166} 167 168 169define void @testsle(i32, i32) { 170; CHECK-LABEL: testsle: 171; CHECK: andi $[[REG0:[0-9]+]], $4, 1 172; CHECK: negu $[[REG2:[0-9]+]], $[[REG0]] 173; CHECK: andi $[[REG1:[0-9]+]], $5, 1 174; CHECK: negu $[[REG3:[0-9]+]], $[[REG1]] 175; CHECK: slt $[[REG4:[0-9]+]], $[[REG3]], $[[REG2]] 176; CHECK: beqz $[[REG4]], 177 %3 = trunc i32 %0 to i1 178 %4 = trunc i32 %1 to i1 179 %5 = icmp sle i1 %3, %4 180 br i1 %5, label %end, label %trap 181trap: 182 call void @llvm.trap() 183 br label %end 184end: 185 ret void 186} 187 188 189declare void @llvm.trap() 190