xref: /llvm-project/llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll (revision 376ab5f413ae9dd2d749a934a087e98e69da600e)
1e4af9de3SPetar Avramovic; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2e4af9de3SPetar Avramovic; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -stop-after=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
3e4af9de3SPetar Avramovic
4e4af9de3SPetar Avramovic; Check there are no COPY instructions surrounding ADDVI_W instruction.
5e4af9de3SPetar Avramovic; All virtual registers were created with createGenericVirtualRegister
6e4af9de3SPetar Avramovic; which sets RegClassOrRegBank in VRegInfo.
7e4af9de3SPetar Avramovic; Constraining register classes when G_INTRINSIC intrinsic(@llvm.mips.addvi.w)
8e4af9de3SPetar Avramovic; gets selected into ADDVI_W works as expected.
9e4af9de3SPetar Avramovic; Check that setRegClassOrRegBank.mir has same output.
10e4af9de3SPetar Avramovic
11e4af9de3SPetar Avramovicdeclare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)
12*376ab5f4SNikita Popovdefine void @add_v4i32_builtin_imm(ptr %a, ptr %c) {
13e4af9de3SPetar Avramovic  ; P5600-LABEL: name: add_v4i32_builtin_imm
14e4af9de3SPetar Avramovic  ; P5600: bb.1.entry:
15e4af9de3SPetar Avramovic  ; P5600:   liveins: $a0, $a1
16e4af9de3SPetar Avramovic  ; P5600:   [[COPY:%[0-9]+]]:_(p0) = COPY $a0
17e4af9de3SPetar Avramovic  ; P5600:   [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
18fae05692SMatt Arsenault  ; P5600:   [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
19e4af9de3SPetar Avramovic  ; P5600:   [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 25
20fae05692SMatt Arsenault  ; P5600:   G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)
21e4af9de3SPetar Avramovic  ; P5600:   RetRA
22e4af9de3SPetar Avramovicentry:
23*376ab5f4SNikita Popov  %0 = load <4 x i32>, ptr %a, align 16
24e4af9de3SPetar Avramovic  %1 = tail call <4 x i32> @llvm.mips.addvi.w(<4 x i32> %0, i32 25)
25*376ab5f4SNikita Popov  store <4 x i32> %1, ptr %c, align 16
26e4af9de3SPetar Avramovic  ret void
27e4af9de3SPetar Avramovic}
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