1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -stop-after=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600 3 4; Check there are no COPY instructions surrounding ADDVI_W instruction. 5; All virtual registers were created with createGenericVirtualRegister 6; which sets RegClassOrRegBank in VRegInfo. 7; Constraining register classes when G_INTRINSIC intrinsic(@llvm.mips.addvi.w) 8; gets selected into ADDVI_W works as expected. 9; Check that setRegClassOrRegBank.mir has same output. 10 11declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg) 12define void @add_v4i32_builtin_imm(ptr %a, ptr %c) { 13 ; P5600-LABEL: name: add_v4i32_builtin_imm 14 ; P5600: bb.1.entry: 15 ; P5600: liveins: $a0, $a1 16 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 17 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1 18 ; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a) 19 ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 25 20 ; P5600: G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c) 21 ; P5600: RetRA 22entry: 23 %0 = load <4 x i32>, ptr %a, align 16 24 %1 = tail call <4 x i32> @llvm.mips.addvi.w(<4 x i32> %0, i32 25) 25 store <4 x i32> %1, ptr %c, align 16 26 ret void 27} 28