xref: /llvm-project/llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9)
1# RUN: not llc -mtriple=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
2
3---
4name: wrong_reg_class_scratch_rsrc_reg
5machineFunctionInfo:
6  scratchRSrcReg:  '$vgpr0_vgpr1_vgpr2_vgpr3'
7# CHECK: :[[@LINE-1]]:{{[0-9]+}}: incorrect register class for field
8body:             |
9  bb.0:
10
11    S_ENDPGM
12...
13