1; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -amdgpu-s-branch-bits=4 -stop-after=branch-relaxation -verify-machineinstrs %s -o - | FileCheck %s 2 3; Test that debug instructions do not change long branch reserved serialized through 4; MIR. 5 6; CHECK-LABEL: {{^}}name: uniform_long_forward_branch_debug 7; CHECK: machineFunctionInfo: 8; CHECK-NEXT: explicitKernArgSize: 12 9; CHECK-NEXT: maxKernArgAlign: 8 10; CHECK-NEXT: ldsSize: 0 11; CHECK-NEXT: gdsSize: 0 12; CHECK-NEXT: dynLDSAlign: 1 13; CHECK-NEXT: isEntryFunction: true 14; CHECK-NEXT: isChainFunction: false 15; CHECK-NEXT: noSignedZerosFPMath: false 16; CHECK-NEXT: memoryBound: false 17; CHECK-NEXT: waveLimiter: false 18; CHECK-NEXT: hasSpilledSGPRs: false 19; CHECK-NEXT: hasSpilledVGPRs: false 20; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' 21; CHECK-NEXT: frameOffsetReg: '$fp_reg' 22; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' 23; CHECK-NEXT: bytesInStackArgArea: 0 24; CHECK-NEXT: returnsVoid: true 25; CHECK-NEXT: argumentInfo: 26; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } 27; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' } 28; CHECK-NEXT: workGroupIDX: { reg: '$sgpr6' } 29; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' } 30; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' } 31; CHECK-NEXT: psInputAddr: 0 32; CHECK-NEXT: psInputEnable: 0 33; CHECK-NEXT: maxMemoryClusterDWords: 8 34; CHECK-NEXT: mode: 35; CHECK-NEXT: ieee: true 36; CHECK-NEXT: dx10-clamp: true 37; CHECK-NEXT: fp32-input-denormals: true 38; CHECK-NEXT: fp32-output-denormals: true 39; CHECK-NEXT: fp64-fp16-input-denormals: true 40; CHECK-NEXT: fp64-fp16-output-denormals: true 41; CHECK-NEXT: BitsOf32BitAddress: 0 42; CHECK-NEXT: occupancy: 10 43; CHECK-NEXT: vgprForAGPRCopy: '' 44; CHECK-NEXT: sgprForEXECCopy: '$sgpr100_sgpr101' 45; CHECK-NEXT: longBranchReservedReg: '$sgpr2_sgpr3' 46; CHECK-NEXT: hasInitWholeWave: false 47; CHECK-NEXT: body: 48 define amdgpu_kernel void @uniform_long_forward_branch_debug(ptr addrspace(1) %arg, i32 %arg1) #0 !dbg !5 { 49 bb0: 50 %uniform_long_forward_branch_debug.kernarg.segment = call nonnull align 16 dereferenceable(12) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr(), !dbg !11 51 %arg1.kernarg.offset = getelementptr inbounds i8, ptr addrspace(4) %uniform_long_forward_branch_debug.kernarg.segment, i64 8, !dbg !11, !amdgpu.uniform !7 52 %arg1.load = load i32, ptr addrspace(4) %arg1.kernarg.offset, align 8, !dbg !11, !invariant.load !7 53 %tmp = icmp eq i32 %arg1.load, 0, !dbg !11 54 call void @llvm.dbg.value(metadata i1 %tmp, metadata !9, metadata !DIExpression()), !dbg !11 55 br i1 %tmp, label %bb3, label %Flow, !dbg !12, !amdgpu.uniform !7 56 57 Flow: ; preds = %bb3, %bb0 58 %0 = phi i1 [ false, %bb3 ], [ true, %bb0 ], !dbg !12 59 br i1 %0, label %bb2, label %bb4, !dbg !12, !amdgpu.uniform !7 60 61 bb2: ; preds = %Flow 62 store volatile i32 17, ptr addrspace(1) undef, align 4, !dbg !13 63 br label %bb4, !dbg !14, !amdgpu.uniform !7 64 65 bb3: ; preds = %bb0 66 call void asm sideeffect "v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64", ""(), !dbg !15 67 br label %Flow, !dbg !16, !amdgpu.uniform !7 68 69 bb4: ; preds = %bb2, %Flow 70 %arg.kernarg.offset1 = bitcast ptr addrspace(4) %uniform_long_forward_branch_debug.kernarg.segment to ptr addrspace(4), !dbg !11, !amdgpu.uniform !7 71 %arg.load = load ptr addrspace(1), ptr addrspace(4) %arg.kernarg.offset1, align 16, !dbg !11, !invariant.load !7 72 store volatile i32 63, ptr addrspace(1) %arg.load, align 4, !dbg !17 73 ret void, !dbg !18 74 } 75 76 ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) 77 declare void @llvm.dbg.value(metadata, metadata, metadata) #1 78 79 ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) 80 declare align 4 ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() #1 81 82 ; Function Attrs: convergent nocallback nofree nounwind willreturn 83 declare { i1, i64 } @llvm.amdgcn.if.i64(i1) #2 84 85 ; Function Attrs: convergent nocallback nofree nounwind willreturn 86 declare { i1, i64 } @llvm.amdgcn.else.i64.i64(i64) #2 87 88 ; Function Attrs: convergent nocallback nofree nounwind willreturn memory(none) 89 declare i64 @llvm.amdgcn.if.break.i64(i1, i64) #3 90 91 ; Function Attrs: convergent nocallback nofree nounwind willreturn 92 declare i1 @llvm.amdgcn.loop.i64(i64) #2 93 94 ; Function Attrs: convergent nocallback nofree nounwind willreturn 95 declare void @llvm.amdgcn.end.cf.i64(i64) #2 96 97 attributes #0 = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 98 attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } 99 attributes #2 = { convergent nocallback nofree nounwind willreturn } 100 attributes #3 = { convergent nocallback nofree nounwind willreturn memory(none) } 101 102 !llvm.dbg.cu = !{!0} 103 !llvm.debugify = !{!2, !3} 104 !llvm.module.flags = !{!4} 105 106 !0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug) 107 !1 = !DIFile(filename: "temp.ll", directory: "/") 108 !2 = !{i32 8} 109 !3 = !{i32 1} 110 !4 = !{i32 2, !"Debug Info Version", i32 3} 111 !5 = distinct !DISubprogram(name: "uniform_long_forward_branch_debug", linkageName: "uniform_long_forward_branch_debug", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8) 112 !6 = !DISubroutineType(types: !7) 113 !7 = !{} 114 !8 = !{!9} 115 !9 = !DILocalVariable(name: "1", scope: !5, file: !1, line: 1, type: !10) 116 !10 = !DIBasicType(name: "ty8", size: 8, encoding: DW_ATE_unsigned) 117 !11 = !DILocation(line: 1, column: 1, scope: !5) 118 !12 = !DILocation(line: 2, column: 1, scope: !5) 119 !13 = !DILocation(line: 3, column: 1, scope: !5) 120 !14 = !DILocation(line: 4, column: 1, scope: !5) 121 !15 = !DILocation(line: 5, column: 1, scope: !5) 122 !16 = !DILocation(line: 6, column: 1, scope: !5) 123 !17 = !DILocation(line: 7, column: 1, scope: !5) 124 !18 = !DILocation(line: 8, column: 1, scope: !5) 125