1; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after finalize-isel -o %t.mir %s 2; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s 3 4; Test that custom pseudo source values can be round trip serialized through MIR. 5 6; CHECK-LABEL: {{^}}name: shader 7; CHECK: %[[#]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET killed %[[#]], %[[#]], 4, 0, 0, implicit $exec :: (dereferenceable load (s32) from %ir.arg3, align 1, addrspace 8) 8; CHECK: IMAGE_STORE_V4_V3_nsa_gfx10 killed %[[#]], %[[#]], %[[#]], %[[#]], killed %[[#]], 15, 2, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), addrspace 8) 9; CHECK: DS_GWS_BARRIER %[[#]], 63, implicit $m0, implicit $exec :: (load (s32) from custom "GWSResource") 10define amdgpu_cs void @shader(i32 %arg0, i32 %arg1, <8 x i32> inreg %arg2, ptr addrspace(8) inreg %arg3) { 11 %bload0 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) %arg3, i32 4, i32 0, i32 0) 12 %bload1 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) %arg3, i32 8, i32 0, i32 0) 13 %bload2 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) %arg3, i32 12, i32 0, i32 0) 14 %bload3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) %arg3, i32 16, i32 0, i32 0) 15 %bload0.f = bitcast i32 %bload0 to float 16 %bload1.f = bitcast i32 %bload1 to float 17 %bload2.f = bitcast i32 %bload2 to float 18 %bload3.f = bitcast i32 %bload3 to float 19 %istore0 = insertelement <4 x float> undef, float %bload0.f, i32 0 20 %istore1 = insertelement <4 x float> %istore0, float %bload0.f, i32 1 21 %istore2 = insertelement <4 x float> %istore1, float %bload0.f, i32 2 22 %istore3 = insertelement <4 x float> %istore2, float %bload0.f, i32 3 23 call void @llvm.amdgcn.image.store.3d.v4f32.i32(<4 x float> %istore3, i32 15, i32 %arg0, i32 %arg1, i32 0, <8 x i32> %arg2, i32 0, i32 0) 24 call void @llvm.amdgcn.ds.gws.barrier(i32 %bload0, i32 63) 25 ret void 26} 27 28declare void @llvm.amdgcn.image.store.3d.v4f32.i32(<4 x float>, i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0 29declare i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8), i32, i32, i32 immarg) #1 30declare void @llvm.amdgcn.ds.gws.barrier(i32, i32) #2 31 32attributes #0 = { nounwind willreturn writeonly } 33attributes #1 = { nounwind memory(argmem: read) willreturn } 34attributes #2 = { convergent inaccessiblememonly nounwind } 35