xref: /llvm-project/llvm/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir (revision 0d63cef180ccc6f5afab824cc784949acb137713)
1# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
2# This test ensures that the MIR parser can parse multiple register machine
3# operands before '='.
4
5# This tests that a MIR file with no vregs does not get altered by mir-canon.
6# RUN: llc -mtriple=aarch64 -o - -run-pass mir-canonicalizer -verify-machineinstrs %s
7
8--- |
9
10  declare void @foo()
11
12  define void @trivial_fp_func() {
13  entry:
14    call void @foo()
15    ret void
16  }
17
18...
19---
20name:            trivial_fp_func
21body: |
22  bb.0.entry:
23    liveins: $lr, $fp, $lr, $fp
24
25    $sp = frame-setup STPXpre killed $fp, killed $lr, $sp, -2
26    $fp = frame-setup ADDXri $sp, 0, 0
27    BL @foo, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
28  ; CHECK: $sp, $fp, $lr = LDPXpost $sp, 2
29    $sp, $fp, $lr = LDPXpost $sp, 2
30    RET_ReallyLR
31...
32