1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s 3 4define void @select_v16i8_imm(ptr %res, ptr %a0) nounwind { 5; CHECK-LABEL: select_v16i8_imm: 6; CHECK: # %bb.0: 7; CHECK-NEXT: vld $vr0, $a1, 0 8; CHECK-NEXT: vrepli.h $vr1, -256 9; CHECK-NEXT: vbitseli.b $vr1, $vr0, 255 10; CHECK-NEXT: vst $vr1, $a0, 0 11; CHECK-NEXT: ret 12 %v0 = load <16 x i8>, ptr %a0 13 %sel = select <16 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %v0 14 store <16 x i8> %sel, ptr %res 15 ret void 16} 17 18define void @select_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { 19; CHECK-LABEL: select_v16i8: 20; CHECK: # %bb.0: 21; CHECK-NEXT: vld $vr0, $a1, 0 22; CHECK-NEXT: vld $vr1, $a2, 0 23; CHECK-NEXT: vrepli.h $vr2, -256 24; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2 25; CHECK-NEXT: vst $vr0, $a0, 0 26; CHECK-NEXT: ret 27 %v0 = load <16 x i8>, ptr %a0 28 %v1 = load <16 x i8>, ptr %a1 29 %sel = select <16 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <16 x i8> %v0, <16 x i8> %v1 30 store <16 x i8> %sel, ptr %res 31 ret void 32} 33 34define void @select_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind { 35; CHECK-LABEL: select_v8i16: 36; CHECK: # %bb.0: 37; CHECK-NEXT: vld $vr0, $a1, 0 38; CHECK-NEXT: vld $vr1, $a2, 0 39; CHECK-NEXT: lu12i.w $a1, -16 40; CHECK-NEXT: vreplgr2vr.w $vr2, $a1 41; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2 42; CHECK-NEXT: vst $vr0, $a0, 0 43; CHECK-NEXT: ret 44 %v0 = load <8 x i16>, ptr %a0 45 %v1 = load <8 x i16>, ptr %a1 46 %sel = select <8 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <8 x i16> %v0, <8 x i16> %v1 47 store <8 x i16> %sel, ptr %res 48 ret void 49} 50 51define void @select_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind { 52; CHECK-LABEL: select_v4i32: 53; CHECK: # %bb.0: 54; CHECK-NEXT: vld $vr0, $a1, 0 55; CHECK-NEXT: vld $vr1, $a2, 0 56; CHECK-NEXT: ori $a1, $zero, 0 57; CHECK-NEXT: lu32i.d $a1, -1 58; CHECK-NEXT: vreplgr2vr.d $vr2, $a1 59; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2 60; CHECK-NEXT: vst $vr0, $a0, 0 61; CHECK-NEXT: ret 62 %v0 = load <4 x i32>, ptr %a0 63 %v1 = load <4 x i32>, ptr %a1 64 %sel = select <4 x i1> <i1 false, i1 true, i1 false, i1 true>, <4 x i32> %v0, <4 x i32> %v1 65 store <4 x i32> %sel, ptr %res 66 ret void 67} 68 69define void @select_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind { 70; CHECK-LABEL: select_v2i64: 71; CHECK: # %bb.0: 72; CHECK-NEXT: vld $vr0, $a1, 0 73; CHECK-NEXT: vld $vr1, $a2, 0 74; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI4_0) 75; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI4_0) 76; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2 77; CHECK-NEXT: vst $vr0, $a0, 0 78; CHECK-NEXT: ret 79 %v0 = load <2 x i64>, ptr %a0 80 %v1 = load <2 x i64>, ptr %a1 81 %sel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %v0, <2 x i64> %v1 82 store <2 x i64> %sel, ptr %res 83 ret void 84} 85