xref: /llvm-project/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil.ll (revision f3aa4416319aed198841401c6c9dc2e49afe2507) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
3
4declare <8 x i16> @llvm.loongarch.lsx.vsllwil.h.b(<16 x i8>, i32)
5
6define <8 x i16> @lsx_vsllwil_h_b(<16 x i8> %va) nounwind {
7; CHECK-LABEL: lsx_vsllwil_h_b:
8; CHECK:       # %bb.0: # %entry
9; CHECK-NEXT:    vsllwil.h.b $vr0, $vr0, 1
10; CHECK-NEXT:    ret
11entry:
12  %res = call <8 x i16> @llvm.loongarch.lsx.vsllwil.h.b(<16 x i8> %va, i32 1)
13  ret <8 x i16> %res
14}
15
16declare <4 x i32> @llvm.loongarch.lsx.vsllwil.w.h(<8 x i16>, i32)
17
18define <4 x i32> @lsx_vsllwil_w_h(<8 x i16> %va) nounwind {
19; CHECK-LABEL: lsx_vsllwil_w_h:
20; CHECK:       # %bb.0: # %entry
21; CHECK-NEXT:    vsllwil.w.h $vr0, $vr0, 1
22; CHECK-NEXT:    ret
23entry:
24  %res = call <4 x i32> @llvm.loongarch.lsx.vsllwil.w.h(<8 x i16> %va, i32 1)
25  ret <4 x i32> %res
26}
27
28declare <2 x i64> @llvm.loongarch.lsx.vsllwil.d.w(<4 x i32>, i32)
29
30define <2 x i64> @lsx_vsllwil_d_w(<4 x i32> %va) nounwind {
31; CHECK-LABEL: lsx_vsllwil_d_w:
32; CHECK:       # %bb.0: # %entry
33; CHECK-NEXT:    vsllwil.d.w $vr0, $vr0, 1
34; CHECK-NEXT:    ret
35entry:
36  %res = call <2 x i64> @llvm.loongarch.lsx.vsllwil.d.w(<4 x i32> %va, i32 1)
37  ret <2 x i64> %res
38}
39
40declare <8 x i16> @llvm.loongarch.lsx.vsllwil.hu.bu(<16 x i8>, i32)
41
42define <8 x i16> @lsx_vsllwil_hu_bu(<16 x i8> %va) nounwind {
43; CHECK-LABEL: lsx_vsllwil_hu_bu:
44; CHECK:       # %bb.0: # %entry
45; CHECK-NEXT:    vsllwil.hu.bu $vr0, $vr0, 7
46; CHECK-NEXT:    ret
47entry:
48  %res = call <8 x i16> @llvm.loongarch.lsx.vsllwil.hu.bu(<16 x i8> %va, i32 7)
49  ret <8 x i16> %res
50}
51
52declare <4 x i32> @llvm.loongarch.lsx.vsllwil.wu.hu(<8 x i16>, i32)
53
54define <4 x i32> @lsx_vsllwil_wu_hu(<8 x i16> %va) nounwind {
55; CHECK-LABEL: lsx_vsllwil_wu_hu:
56; CHECK:       # %bb.0: # %entry
57; CHECK-NEXT:    vsllwil.wu.hu $vr0, $vr0, 15
58; CHECK-NEXT:    ret
59entry:
60  %res = call <4 x i32> @llvm.loongarch.lsx.vsllwil.wu.hu(<8 x i16> %va, i32 15)
61  ret <4 x i32> %res
62}
63
64declare <2 x i64> @llvm.loongarch.lsx.vsllwil.du.wu(<4 x i32>, i32)
65
66define <2 x i64> @lsx_vsllwil_du_wu(<4 x i32> %va) nounwind {
67; CHECK-LABEL: lsx_vsllwil_du_wu:
68; CHECK:       # %bb.0: # %entry
69; CHECK-NEXT:    vsllwil.du.wu $vr0, $vr0, 31
70; CHECK-NEXT:    ret
71entry:
72  %res = call <2 x i64> @llvm.loongarch.lsx.vsllwil.du.wu(<4 x i32> %va, i32 31)
73  ret <2 x i64> %res
74}
75