1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s 3 4declare <16 x i8> @llvm.loongarch.lsx.vreplgr2vr.b(i32) 5 6define <16 x i8> @lsx_vreplgr2vr_b(i32 %a) nounwind { 7; CHECK-LABEL: lsx_vreplgr2vr_b: 8; CHECK: # %bb.0: # %entry 9; CHECK-NEXT: vreplgr2vr.b $vr0, $a0 10; CHECK-NEXT: ret 11entry: 12 %res = call <16 x i8> @llvm.loongarch.lsx.vreplgr2vr.b(i32 %a) 13 ret <16 x i8> %res 14} 15 16declare <8 x i16> @llvm.loongarch.lsx.vreplgr2vr.h(i32) 17 18define <8 x i16> @lsx_vreplgr2vr_h(i32 %a) nounwind { 19; CHECK-LABEL: lsx_vreplgr2vr_h: 20; CHECK: # %bb.0: # %entry 21; CHECK-NEXT: vreplgr2vr.h $vr0, $a0 22; CHECK-NEXT: ret 23entry: 24 %res = call <8 x i16> @llvm.loongarch.lsx.vreplgr2vr.h(i32 %a) 25 ret <8 x i16> %res 26} 27 28declare <4 x i32> @llvm.loongarch.lsx.vreplgr2vr.w(i32) 29 30define <4 x i32> @lsx_vreplgr2vr_w(i32 %a) nounwind { 31; CHECK-LABEL: lsx_vreplgr2vr_w: 32; CHECK: # %bb.0: # %entry 33; CHECK-NEXT: vreplgr2vr.w $vr0, $a0 34; CHECK-NEXT: ret 35entry: 36 %res = call <4 x i32> @llvm.loongarch.lsx.vreplgr2vr.w(i32 %a) 37 ret <4 x i32> %res 38} 39 40declare <2 x i64> @llvm.loongarch.lsx.vreplgr2vr.d(i64) 41 42define <2 x i64> @lsx_vreplgr2vr_d(i64 %a) nounwind { 43; CHECK-LABEL: lsx_vreplgr2vr_d: 44; CHECK: # %bb.0: # %entry 45; CHECK-NEXT: vreplgr2vr.d $vr0, $a0 46; CHECK-NEXT: ret 47entry: 48 %res = call <2 x i64> @llvm.loongarch.lsx.vreplgr2vr.d(i64 %a) 49 ret <2 x i64> %res 50} 51