xref: /llvm-project/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins.ll (revision f3aa4416319aed198841401c6c9dc2e49afe2507) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
3
4declare <16 x i8> @llvm.loongarch.lsx.vextrins.b(<16 x i8>, <16 x i8>, i32)
5
6define <16 x i8> @lsx_vextrins_b(<16 x i8> %va, <16 x i8> %vb) nounwind {
7; CHECK-LABEL: lsx_vextrins_b:
8; CHECK:       # %bb.0: # %entry
9; CHECK-NEXT:    vextrins.b $vr0, $vr1, 255
10; CHECK-NEXT:    ret
11entry:
12  %res = call <16 x i8> @llvm.loongarch.lsx.vextrins.b(<16 x i8> %va, <16 x i8> %vb, i32 255)
13  ret <16 x i8> %res
14}
15
16declare <8 x i16> @llvm.loongarch.lsx.vextrins.h(<8 x i16>, <8 x i16>, i32)
17
18define <8 x i16> @lsx_vextrins_h(<8 x i16> %va, <8 x i16> %vb) nounwind {
19; CHECK-LABEL: lsx_vextrins_h:
20; CHECK:       # %bb.0: # %entry
21; CHECK-NEXT:    vextrins.h $vr0, $vr1, 255
22; CHECK-NEXT:    ret
23entry:
24  %res = call <8 x i16> @llvm.loongarch.lsx.vextrins.h(<8 x i16> %va, <8 x i16> %vb, i32 255)
25  ret <8 x i16> %res
26}
27
28declare <4 x i32> @llvm.loongarch.lsx.vextrins.w(<4 x i32>, <4 x i32>, i32)
29
30define <4 x i32> @lsx_vextrins_w(<4 x i32> %va, <4 x i32> %vb) nounwind {
31; CHECK-LABEL: lsx_vextrins_w:
32; CHECK:       # %bb.0: # %entry
33; CHECK-NEXT:    vextrins.w $vr0, $vr1, 255
34; CHECK-NEXT:    ret
35entry:
36  %res = call <4 x i32> @llvm.loongarch.lsx.vextrins.w(<4 x i32> %va, <4 x i32> %vb, i32 255)
37  ret <4 x i32> %res
38}
39
40declare <2 x i64> @llvm.loongarch.lsx.vextrins.d(<2 x i64>, <2 x i64>, i32)
41
42define <2 x i64> @lsx_vextrins_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
43; CHECK-LABEL: lsx_vextrins_d:
44; CHECK:       # %bb.0: # %entry
45; CHECK-NEXT:    vextrins.d $vr0, $vr1, 255
46; CHECK-NEXT:    ret
47entry:
48  %res = call <2 x i64> @llvm.loongarch.lsx.vextrins.d(<2 x i64> %va, <2 x i64> %vb, i32 255)
49  ret <2 x i64> %res
50}
51