xref: /llvm-project/llvm/test/CodeGen/LoongArch/lsx/intrinsic-exth.ll (revision f3aa4416319aed198841401c6c9dc2e49afe2507) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
3
4declare <8 x i16> @llvm.loongarch.lsx.vexth.h.b(<16 x i8>)
5
6define <8 x i16> @lsx_vexth_h_b(<16 x i8> %va) nounwind {
7; CHECK-LABEL: lsx_vexth_h_b:
8; CHECK:       # %bb.0: # %entry
9; CHECK-NEXT:    vexth.h.b $vr0, $vr0
10; CHECK-NEXT:    ret
11entry:
12  %res = call <8 x i16> @llvm.loongarch.lsx.vexth.h.b(<16 x i8> %va)
13  ret <8 x i16> %res
14}
15
16declare <4 x i32> @llvm.loongarch.lsx.vexth.w.h(<8 x i16>)
17
18define <4 x i32> @lsx_vexth_w_h(<8 x i16> %va) nounwind {
19; CHECK-LABEL: lsx_vexth_w_h:
20; CHECK:       # %bb.0: # %entry
21; CHECK-NEXT:    vexth.w.h $vr0, $vr0
22; CHECK-NEXT:    ret
23entry:
24  %res = call <4 x i32> @llvm.loongarch.lsx.vexth.w.h(<8 x i16> %va)
25  ret <4 x i32> %res
26}
27
28declare <2 x i64> @llvm.loongarch.lsx.vexth.d.w(<4 x i32>)
29
30define <2 x i64> @lsx_vexth_d_w(<4 x i32> %va) nounwind {
31; CHECK-LABEL: lsx_vexth_d_w:
32; CHECK:       # %bb.0: # %entry
33; CHECK-NEXT:    vexth.d.w $vr0, $vr0
34; CHECK-NEXT:    ret
35entry:
36  %res = call <2 x i64> @llvm.loongarch.lsx.vexth.d.w(<4 x i32> %va)
37  ret <2 x i64> %res
38}
39
40declare <2 x i64> @llvm.loongarch.lsx.vexth.q.d(<2 x i64>)
41
42define <2 x i64> @lsx_vexth_q_d(<2 x i64> %va) nounwind {
43; CHECK-LABEL: lsx_vexth_q_d:
44; CHECK:       # %bb.0: # %entry
45; CHECK-NEXT:    vexth.q.d $vr0, $vr0
46; CHECK-NEXT:    ret
47entry:
48  %res = call <2 x i64> @llvm.loongarch.lsx.vexth.q.d(<2 x i64> %va)
49  ret <2 x i64> %res
50}
51
52declare <8 x i16> @llvm.loongarch.lsx.vexth.hu.bu(<16 x i8>)
53
54define <8 x i16> @lsx_vexth_hu_bu(<16 x i8> %va) nounwind {
55; CHECK-LABEL: lsx_vexth_hu_bu:
56; CHECK:       # %bb.0: # %entry
57; CHECK-NEXT:    vexth.hu.bu $vr0, $vr0
58; CHECK-NEXT:    ret
59entry:
60  %res = call <8 x i16> @llvm.loongarch.lsx.vexth.hu.bu(<16 x i8> %va)
61  ret <8 x i16> %res
62}
63
64declare <4 x i32> @llvm.loongarch.lsx.vexth.wu.hu(<8 x i16>)
65
66define <4 x i32> @lsx_vexth_wu_hu(<8 x i16> %va) nounwind {
67; CHECK-LABEL: lsx_vexth_wu_hu:
68; CHECK:       # %bb.0: # %entry
69; CHECK-NEXT:    vexth.wu.hu $vr0, $vr0
70; CHECK-NEXT:    ret
71entry:
72  %res = call <4 x i32> @llvm.loongarch.lsx.vexth.wu.hu(<8 x i16> %va)
73  ret <4 x i32> %res
74}
75
76declare <2 x i64> @llvm.loongarch.lsx.vexth.du.wu(<4 x i32>)
77
78define <2 x i64> @lsx_vexth_du_wu(<4 x i32> %va) nounwind {
79; CHECK-LABEL: lsx_vexth_du_wu:
80; CHECK:       # %bb.0: # %entry
81; CHECK-NEXT:    vexth.du.wu $vr0, $vr0
82; CHECK-NEXT:    ret
83entry:
84  %res = call <2 x i64> @llvm.loongarch.lsx.vexth.du.wu(<4 x i32> %va)
85  ret <2 x i64> %res
86}
87
88declare <2 x i64> @llvm.loongarch.lsx.vexth.qu.du(<2 x i64>)
89
90define <2 x i64> @lsx_vexth_qu_du(<2 x i64> %va) nounwind {
91; CHECK-LABEL: lsx_vexth_qu_du:
92; CHECK:       # %bb.0: # %entry
93; CHECK-NEXT:    vexth.qu.du $vr0, $vr0
94; CHECK-NEXT:    ret
95entry:
96  %res = call <2 x i64> @llvm.loongarch.lsx.vexth.qu.du(<2 x i64> %va)
97  ret <2 x i64> %res
98}
99