1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 2; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s 3 4define void @buildvector_v16i8_splat(ptr %dst, i8 %a0) nounwind { 5; CHECK-LABEL: buildvector_v16i8_splat: 6; CHECK: # %bb.0: # %entry 7; CHECK-NEXT: vreplgr2vr.b $vr0, $a1 8; CHECK-NEXT: vst $vr0, $a0, 0 9; CHECK-NEXT: ret 10entry: 11 %insert = insertelement <16 x i8> undef, i8 %a0, i8 0 12 %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer 13 store <16 x i8> %splat, ptr %dst 14 ret void 15} 16 17define void @buildvector_v8i16_splat(ptr %dst, i16 %a0) nounwind { 18; CHECK-LABEL: buildvector_v8i16_splat: 19; CHECK: # %bb.0: # %entry 20; CHECK-NEXT: vreplgr2vr.h $vr0, $a1 21; CHECK-NEXT: vst $vr0, $a0, 0 22; CHECK-NEXT: ret 23entry: 24 %insert = insertelement <8 x i16> undef, i16 %a0, i8 0 25 %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer 26 store <8 x i16> %splat, ptr %dst 27 ret void 28} 29 30define void @buildvector_v4i32_splat(ptr %dst, i32 %a0) nounwind { 31; CHECK-LABEL: buildvector_v4i32_splat: 32; CHECK: # %bb.0: # %entry 33; CHECK-NEXT: vreplgr2vr.w $vr0, $a1 34; CHECK-NEXT: vst $vr0, $a0, 0 35; CHECK-NEXT: ret 36entry: 37 %insert = insertelement <4 x i32> undef, i32 %a0, i8 0 38 %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer 39 store <4 x i32> %splat, ptr %dst 40 ret void 41} 42 43define void @buildvector_v2i64_splat(ptr %dst, i64 %a0) nounwind { 44; CHECK-LABEL: buildvector_v2i64_splat: 45; CHECK: # %bb.0: # %entry 46; CHECK-NEXT: vreplgr2vr.d $vr0, $a1 47; CHECK-NEXT: vst $vr0, $a0, 0 48; CHECK-NEXT: ret 49entry: 50 %insert = insertelement <2 x i64> undef, i64 %a0, i8 0 51 %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer 52 store <2 x i64> %splat, ptr %dst 53 ret void 54} 55 56define void @buildvector_v4f32_splat(ptr %dst, float %a0) nounwind { 57; CHECK-LABEL: buildvector_v4f32_splat: 58; CHECK: # %bb.0: # %entry 59; CHECK-NEXT: # kill: def $f0 killed $f0 def $vr0 60; CHECK-NEXT: vreplvei.w $vr0, $vr0, 0 61; CHECK-NEXT: vst $vr0, $a0, 0 62; CHECK-NEXT: ret 63entry: 64 %insert = insertelement <4 x float> undef, float %a0, i8 0 65 %splat = shufflevector <4 x float> %insert, <4 x float> undef, <4 x i32> zeroinitializer 66 store <4 x float> %splat, ptr %dst 67 ret void 68} 69 70define void @buildvector_v2f64_splat(ptr %dst, double %a0) nounwind { 71; CHECK-LABEL: buildvector_v2f64_splat: 72; CHECK: # %bb.0: # %entry 73; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0 74; CHECK-NEXT: vreplvei.d $vr0, $vr0, 0 75; CHECK-NEXT: vst $vr0, $a0, 0 76; CHECK-NEXT: ret 77entry: 78 %insert = insertelement <2 x double> undef, double %a0, i8 0 79 %splat = shufflevector <2 x double> %insert, <2 x double> undef, <2 x i32> zeroinitializer 80 store <2 x double> %splat, ptr %dst 81 ret void 82} 83 84define void @buildvector_v16i8_const_splat(ptr %dst) nounwind { 85; CHECK-LABEL: buildvector_v16i8_const_splat: 86; CHECK: # %bb.0: # %entry 87; CHECK-NEXT: vrepli.b $vr0, 1 88; CHECK-NEXT: vst $vr0, $a0, 0 89; CHECK-NEXT: ret 90entry: 91 store <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, ptr %dst 92 ret void 93} 94 95define void @buildvector_v8i16_const_splat(ptr %dst) nounwind { 96; CHECK-LABEL: buildvector_v8i16_const_splat: 97; CHECK: # %bb.0: # %entry 98; CHECK-NEXT: vrepli.h $vr0, 1 99; CHECK-NEXT: vst $vr0, $a0, 0 100; CHECK-NEXT: ret 101entry: 102 store <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, ptr %dst 103 ret void 104} 105 106define void @buildvector_v4i32_const_splat(ptr %dst) nounwind { 107; CHECK-LABEL: buildvector_v4i32_const_splat: 108; CHECK: # %bb.0: # %entry 109; CHECK-NEXT: vrepli.w $vr0, 1 110; CHECK-NEXT: vst $vr0, $a0, 0 111; CHECK-NEXT: ret 112entry: 113 store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, ptr %dst 114 ret void 115} 116 117define void @buildvector_v2i64_const_splat(ptr %dst) nounwind { 118; CHECK-LABEL: buildvector_v2i64_const_splat: 119; CHECK: # %bb.0: # %entry 120; CHECK-NEXT: vrepli.d $vr0, 1 121; CHECK-NEXT: vst $vr0, $a0, 0 122; CHECK-NEXT: ret 123entry: 124 store <2 x i64> <i64 1, i64 1>, ptr %dst 125 ret void 126} 127 128define void @buildvector_v2f32_const_splat(ptr %dst) nounwind { 129; CHECK-LABEL: buildvector_v2f32_const_splat: 130; CHECK: # %bb.0: # %entry 131; CHECK-NEXT: lu12i.w $a1, 260096 132; CHECK-NEXT: vreplgr2vr.w $vr0, $a1 133; CHECK-NEXT: vst $vr0, $a0, 0 134; CHECK-NEXT: ret 135entry: 136 store <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, ptr %dst 137 ret void 138} 139 140define void @buildvector_v2f64_const_splat(ptr %dst) nounwind { 141; CHECK-LABEL: buildvector_v2f64_const_splat: 142; CHECK: # %bb.0: # %entry 143; CHECK-NEXT: lu52i.d $a1, $zero, 1023 144; CHECK-NEXT: vreplgr2vr.d $vr0, $a1 145; CHECK-NEXT: vst $vr0, $a0, 0 146; CHECK-NEXT: ret 147entry: 148 store <2 x double> <double 1.0, double 1.0>, ptr %dst 149 ret void 150} 151 152define void @buildvector_v16i8_const(ptr %dst) nounwind { 153; CHECK-LABEL: buildvector_v16i8_const: 154; CHECK: # %bb.0: # %entry 155; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI12_0) 156; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI12_0) 157; CHECK-NEXT: vst $vr0, $a0, 0 158; CHECK-NEXT: ret 159entry: 160 store <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, ptr %dst 161 ret void 162} 163 164define void @buildvector_v8i16_const(ptr %dst) nounwind { 165; CHECK-LABEL: buildvector_v8i16_const: 166; CHECK: # %bb.0: # %entry 167; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI13_0) 168; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI13_0) 169; CHECK-NEXT: vst $vr0, $a0, 0 170; CHECK-NEXT: ret 171entry: 172 store <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, ptr %dst 173 ret void 174} 175 176define void @buildvector_v4i32_const(ptr %dst) nounwind { 177; CHECK-LABEL: buildvector_v4i32_const: 178; CHECK: # %bb.0: # %entry 179; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI14_0) 180; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI14_0) 181; CHECK-NEXT: vst $vr0, $a0, 0 182; CHECK-NEXT: ret 183entry: 184 store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, ptr %dst 185 ret void 186} 187 188define void @buildvector_v2i64_const(ptr %dst) nounwind { 189; CHECK-LABEL: buildvector_v2i64_const: 190; CHECK: # %bb.0: # %entry 191; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI15_0) 192; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI15_0) 193; CHECK-NEXT: vst $vr0, $a0, 0 194; CHECK-NEXT: ret 195entry: 196 store <2 x i64> <i64 0, i64 1>, ptr %dst 197 ret void 198} 199 200define void @buildvector_v2f32_const(ptr %dst) nounwind { 201; CHECK-LABEL: buildvector_v2f32_const: 202; CHECK: # %bb.0: # %entry 203; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI16_0) 204; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI16_0) 205; CHECK-NEXT: vst $vr0, $a0, 0 206; CHECK-NEXT: ret 207entry: 208 store <4 x float> <float 0.0, float 1.0, float 2.0, float 3.0>, ptr %dst 209 ret void 210} 211 212define void @buildvector_v2f64_const(ptr %dst) nounwind { 213; CHECK-LABEL: buildvector_v2f64_const: 214; CHECK: # %bb.0: # %entry 215; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI17_0) 216; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI17_0) 217; CHECK-NEXT: vst $vr0, $a0, 0 218; CHECK-NEXT: ret 219entry: 220 store <2 x double> <double 0.0, double 1.0>, ptr %dst 221 ret void 222} 223 224define void @buildvector_v16i8(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15) nounwind { 225; CHECK-LABEL: buildvector_v16i8: 226; CHECK: # %bb.0: # %entry 227; CHECK-NEXT: ld.b $t0, $sp, 64 228; CHECK-NEXT: ld.b $t1, $sp, 56 229; CHECK-NEXT: ld.b $t2, $sp, 48 230; CHECK-NEXT: ld.b $t3, $sp, 40 231; CHECK-NEXT: ld.b $t4, $sp, 32 232; CHECK-NEXT: ld.b $t5, $sp, 24 233; CHECK-NEXT: ld.b $t6, $sp, 16 234; CHECK-NEXT: ld.b $t7, $sp, 8 235; CHECK-NEXT: ld.b $t8, $sp, 0 236; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0 237; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 1 238; CHECK-NEXT: vinsgr2vr.b $vr0, $a3, 2 239; CHECK-NEXT: vinsgr2vr.b $vr0, $a4, 3 240; CHECK-NEXT: vinsgr2vr.b $vr0, $a5, 4 241; CHECK-NEXT: vinsgr2vr.b $vr0, $a6, 5 242; CHECK-NEXT: vinsgr2vr.b $vr0, $a7, 6 243; CHECK-NEXT: vinsgr2vr.b $vr0, $t8, 7 244; CHECK-NEXT: vinsgr2vr.b $vr0, $t7, 8 245; CHECK-NEXT: vinsgr2vr.b $vr0, $t6, 9 246; CHECK-NEXT: vinsgr2vr.b $vr0, $t5, 10 247; CHECK-NEXT: vinsgr2vr.b $vr0, $t4, 11 248; CHECK-NEXT: vinsgr2vr.b $vr0, $t3, 12 249; CHECK-NEXT: vinsgr2vr.b $vr0, $t2, 13 250; CHECK-NEXT: vinsgr2vr.b $vr0, $t1, 14 251; CHECK-NEXT: vinsgr2vr.b $vr0, $t0, 15 252; CHECK-NEXT: vst $vr0, $a0, 0 253; CHECK-NEXT: ret 254entry: 255 %ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0 256 %ins1 = insertelement <16 x i8> %ins0, i8 %a1, i32 1 257 %ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2 258 %ins3 = insertelement <16 x i8> %ins2, i8 %a3, i32 3 259 %ins4 = insertelement <16 x i8> %ins3, i8 %a4, i32 4 260 %ins5 = insertelement <16 x i8> %ins4, i8 %a5, i32 5 261 %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6 262 %ins7 = insertelement <16 x i8> %ins6, i8 %a7, i32 7 263 %ins8 = insertelement <16 x i8> %ins7, i8 %a8, i32 8 264 %ins9 = insertelement <16 x i8> %ins8, i8 %a9, i32 9 265 %ins10 = insertelement <16 x i8> %ins9, i8 %a10, i32 10 266 %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11 267 %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12 268 %ins13 = insertelement <16 x i8> %ins12, i8 %a13, i32 13 269 %ins14 = insertelement <16 x i8> %ins13, i8 %a14, i32 14 270 %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15 271 store <16 x i8> %ins15, ptr %dst 272 ret void 273} 274 275define void @buildvector_v8i16(ptr %dst, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind { 276; CHECK-LABEL: buildvector_v8i16: 277; CHECK: # %bb.0: # %entry 278; CHECK-NEXT: ld.h $t0, $sp, 0 279; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 0 280; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 1 281; CHECK-NEXT: vinsgr2vr.h $vr0, $a3, 2 282; CHECK-NEXT: vinsgr2vr.h $vr0, $a4, 3 283; CHECK-NEXT: vinsgr2vr.h $vr0, $a5, 4 284; CHECK-NEXT: vinsgr2vr.h $vr0, $a6, 5 285; CHECK-NEXT: vinsgr2vr.h $vr0, $a7, 6 286; CHECK-NEXT: vinsgr2vr.h $vr0, $t0, 7 287; CHECK-NEXT: vst $vr0, $a0, 0 288; CHECK-NEXT: ret 289entry: 290 %ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0 291 %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1 292 %ins2 = insertelement <8 x i16> %ins1, i16 %a2, i32 2 293 %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3 294 %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4 295 %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5 296 %ins6 = insertelement <8 x i16> %ins5, i16 %a6, i32 6 297 %ins7 = insertelement <8 x i16> %ins6, i16 %a7, i32 7 298 store <8 x i16> %ins7, ptr %dst 299 ret void 300} 301 302define void @buildvector_v4i32(ptr %dst, i32 %a0, i32 %a1, i32 %a2, i32 %a3) nounwind { 303; CHECK-LABEL: buildvector_v4i32: 304; CHECK: # %bb.0: # %entry 305; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 0 306; CHECK-NEXT: vinsgr2vr.w $vr0, $a2, 1 307; CHECK-NEXT: vinsgr2vr.w $vr0, $a3, 2 308; CHECK-NEXT: vinsgr2vr.w $vr0, $a4, 3 309; CHECK-NEXT: vst $vr0, $a0, 0 310; CHECK-NEXT: ret 311entry: 312 %ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0 313 %ins1 = insertelement <4 x i32> %ins0, i32 %a1, i32 1 314 %ins2 = insertelement <4 x i32> %ins1, i32 %a2, i32 2 315 %ins3 = insertelement <4 x i32> %ins2, i32 %a3, i32 3 316 store <4 x i32> %ins3, ptr %dst 317 ret void 318} 319 320define void @buildvector_v2i64(ptr %dst, i64 %a0, i64 %a1) nounwind { 321; CHECK-LABEL: buildvector_v2i64: 322; CHECK: # %bb.0: # %entry 323; CHECK-NEXT: vinsgr2vr.d $vr0, $a1, 0 324; CHECK-NEXT: vinsgr2vr.d $vr0, $a2, 1 325; CHECK-NEXT: vst $vr0, $a0, 0 326; CHECK-NEXT: ret 327entry: 328 %ins0 = insertelement <2 x i64> undef, i64 %a0, i32 0 329 %ins1 = insertelement <2 x i64> %ins0, i64 %a1, i32 1 330 store <2 x i64> %ins1, ptr %dst 331 ret void 332} 333 334define void @buildvector_v4f32(ptr %dst, float %a0, float %a1, float %a2, float %a3) nounwind { 335; CHECK-LABEL: buildvector_v4f32: 336; CHECK: # %bb.0: # %entry 337; CHECK-NEXT: movfr2gr.s $a1, $fa0 338; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 0 339; CHECK-NEXT: movfr2gr.s $a1, $fa1 340; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 1 341; CHECK-NEXT: movfr2gr.s $a1, $fa2 342; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 2 343; CHECK-NEXT: movfr2gr.s $a1, $fa3 344; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 3 345; CHECK-NEXT: vst $vr0, $a0, 0 346; CHECK-NEXT: ret 347entry: 348 %ins0 = insertelement <4 x float> undef, float %a0, i32 0 349 %ins1 = insertelement <4 x float> %ins0, float %a1, i32 1 350 %ins2 = insertelement <4 x float> %ins1, float %a2, i32 2 351 %ins3 = insertelement <4 x float> %ins2, float %a3, i32 3 352 store <4 x float> %ins3, ptr %dst 353 ret void 354} 355 356define void @buildvector_v2f64(ptr %dst, double %a0, double %a1) nounwind { 357; CHECK-LABEL: buildvector_v2f64: 358; CHECK: # %bb.0: # %entry 359; CHECK-NEXT: movfr2gr.d $a1, $fa0 360; CHECK-NEXT: vinsgr2vr.d $vr0, $a1, 0 361; CHECK-NEXT: movfr2gr.d $a1, $fa1 362; CHECK-NEXT: vinsgr2vr.d $vr0, $a1, 1 363; CHECK-NEXT: vst $vr0, $a0, 0 364; CHECK-NEXT: ret 365entry: 366 %ins0 = insertelement <2 x double> undef, double %a0, i32 0 367 %ins1 = insertelement <2 x double> %ins0, double %a1, i32 1 368 store <2 x double> %ins1, ptr %dst 369 ret void 370} 371 372;; If `isShuffleMaskLegal` returns true, it will lead to an infinite loop. 373define void @extract1_i32_zext_insert0_i64_undef(ptr %src, ptr %dst) nounwind { 374; CHECK-LABEL: extract1_i32_zext_insert0_i64_undef: 375; CHECK: # %bb.0: 376; CHECK-NEXT: vld $vr0, $a0, 0 377; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 1 378; CHECK-NEXT: bstrpick.d $a0, $a0, 31, 0 379; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 380; CHECK-NEXT: vst $vr0, $a1, 0 381; CHECK-NEXT: ret 382 %v = load volatile <4 x i32>, ptr %src 383 %e = extractelement <4 x i32> %v, i32 1 384 %z = zext i32 %e to i64 385 %r = insertelement <2 x i64> undef, i64 %z, i32 0 386 store <2 x i64> %r, ptr %dst 387 ret void 388} 389